A 2.4–3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration

Lu, Yong-Ru; Liu, Shen-Iuan; Yang, Ya-Chien; Kang, Han-Chang; Chen, Chih-Lung; Chan, Ka-Un; Lin, Ying-Hsi

doi:10.1109/tcsii.2020.3022833

Cited by 5 publications

(2 citation statements)

References 17 publications

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“…In dynamic random-access memory (DRAM), dual in-line memory modules (DIMMs) are still used for low cost and high memory capacity. To solve the clock skew problem associated with the on-chip clock distribution network and the use of DIMMs in the memory bus, DLL [1][2][3] and phase-locked loop (PLL) [4][5][6][7] are used to generate clock signals in phase with the external input clock, synchronizing internal data transfer in DRAM with the external controller clock [8]. DLLs are an important part of modern DRAM technology because they enable high-speed data transfer rates while ensuring data accuracy and reliability.…”

Section: Introductionmentioning

confidence: 99%

A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range

et al. 2023

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This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The proposed DLL adopted a dual delay line structure, each delay line was composed of a coarse adjustment and a fine adjustment unit, and the dual delay lines had corresponding control units to reduce the mismatch between the delay lines, and it avoided the complicated design of duty cycle correction (DCC) circuit. A frequency divider was added to divide the input clock to achieve a wider input clock duty cycle adjustment. Additionally, a simple clock synthesis circuit was proposed to synthesize the required clock. The DLL design used the 25 nm process with a voltage of 1.2 V. The simulation results showed that at a working frequency of 1.6 GHz, the peak-to-peak jitter of the DC-DL DLL after locking was approximately 17.61 ps, the maximum output duty cycle error was about 1.3%, and the input duty cycle ranged from 20% to 80%, with a power consumption of 10.06 mW.

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Section: Introductionmentioning

confidence: 99%

A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range

et al. 2023

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“…To guarantee proper filtering of phase noise sources and stable phase noise profile, real products require methods to compensate the spread of several parameters. While the frequency of the reference typically obtained from a quartz crystal has good stability and the frequency division in the loop is exact, the loop filter, the phase-detector gain and the voltagecontrolled-oscillator (VCO) sensitivity are subject to process, voltage and temperature [1]. Furthermore, VCO sensitivity is also a function of the synthesized frequency, as any practical VCO exhibits a voltageto-frequency characteristic significantly nonlinear.…”

Section: Introductionmentioning

confidence: 99%

A Digital PLL With Multitap LMS-Based Bandwidth Control

Mercandelli

Bertulessi

Samori

et al. 2022

IEEE Solid-State Circuits Lett.

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Automatic bandwidth control based on least-mean-square adaptive filters has been demonstrated to desensitize the loop gain of a phase-locked loop from process spreads, environmental variations and channel frequency. This work extends this concept to low-jitter designs that adopts aggressive out-of-band filtering, by introducing multitap adaptive filtering. The method requires no injection of a training sequence, potentially degrading phase noise, and it is particularly suitable for bang-bang PLLs whose loop bandwidth depends on input noise. A 3.7-to-4.1-GHz PLL prototype embedding a 16-tap adaptive filter for loop gain estimation demonstrates 150-kHz loop bandwidth over input noise and voltage supply variations, at 183-fs RMS integrated jitter and 5.3-mW power consumption.

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A current-configurable charge pump with current mismatch compensation for wide output frequency range phase-locked loop

Han,

Tong

2024

AEU - International Journal of Electronics and Communications

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A 2.4–3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration

Cited by 5 publications

References 17 publications

A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range

A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range

A Digital PLL With Multitap LMS-Based Bandwidth Control

A current-configurable charge pump with current mismatch compensation for wide output frequency range phase-locked loop

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