A 16b 80MS/s 100mW 77.6dB SNR CMOS pipeline ADC

A 1.2 V 10-bit 60-MS/s 23 mW CMOS pipeline ADC with 0.67 pJ/conversion-step and on-chip reference voltages generator

“…Four main reasons make this design procedure in a powerful and efficient synthesis methodology: (1) the behavioral models of the basic building blocks are, to the best of our knowledge, the more accurate reported up to date, modeling both one-and two-stage OTA topologies and large-and small-signal effects [23]; actually, behavioral simulations show less than 0.3-bit deviation in relation to transistor-level simulations, as shown in [14], (2) the design space, which can involve more than 20 variables per stage, is drastically reduced to only three design variables; otherwise, handling the dozens of parameters would render any optimization process inefficient and prone to get trapped in local minima, (3) the transistor-level mapping algorithm employs information extracted from the technological process by means of look-up tables which have been previously generated from batches of Spectre Ò runs, to guarantee technological feasibility of the sized circuits and accurate estimations of parasitics and other transistorlevel parameters, and (4) the mapping of the high-level converter specifications on low-level transistor-level parameters is carried out in a single procedure, reducing drastically the design cycle and user iterations. .…”

“…Pipeline ADCs have demonstrated to be a good solution to solve the accuracy-speed trade-off for medium-high resolution converters [1,2]. Since reducing the power consumption is an important challenge for Systems-on-Chip (SoC) implementation, different power reduction techniques suitable for pipeline data converters have been proposed, such as, opamp sharing [3,4], S&H removal [5,6], switched-opamp techniques [7,8] pseudo-differential architectures [9] or digital calibration [10,11].…”

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

“…The change of parasitic capacitance in the proposed structure is a half compared with [29]. In structure [30], three auxiliary switches are used and unnecessary parasitic capacitance of sampling switch will increase obviously. The total parasitic capacitance is also depressed compared with [31], in which, the parasitic capacitance and compensation capacitance are in parallel.…”

“…A buffered bootstrapping technique is provided in [29] to reduce signal-dependent charge injection in the design of sampling switch. A high linearity technique is introduced in [30] to reduce the parasitic capacitance of sampling switch. But three auxiliary switches are needed and more parasitic capacitances are imported.…”

A Replica-Driving Technique for High Performance SC Circuits and Pipelined ADC Design

“…However, the increased number of cycles in the amplification phase and the oscillation property limit the conversion speed to some extent. Even though it is clear that the recent research trend for pipelined ADCs is to avoid the use of an opamp, high performance pipelined ADCs still rely heavily on opamps [6], [7] due to the limitations of the aforementioned low power techniques. In this paper, for opamp-based high performance pipelined ADCs, we present a low-power closed-loop amplifier design technique that advances the replica-driving scheme, examples of which can be found in previous reference drivers [8], [9].…”