A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation

Atsumi, S.; Kuriyama, M.; Umezawa, Akira; Banba, H.; Naruke, K.; Yamada, Shigeru; Ohshima, Y.; Oshikiri, M.; Hiura, Y.; Yamane, Takeshi; Yoshikawa, K.

doi:10.1109/4.280696

Cited by 42 publications

(12 citation statements)

References 12 publications

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“…This facilitates higher charge transfer for subsequent stages. This concept of augmenting internal node voltages > V DD has been demonstrated in Flash memories (Umezawa et al, 1992;Atsumi et al, 1994). The Bootstrap CP (Fig.…”

Section: Bootstrap Charge Pumpmentioning

confidence: 99%

Review of Charge Pump Topologies for Micro Energy Harvesting Systems

Mi¹,

Islam

Sampe

et al. 2016

American Journal of Applied Sciences

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This paper reviews CMOS based charge pump topologies used within autonomous embedded micro-systems. These charge pump structures have evolved from its simplistic diode-tied, single-branches with major threshold drops to exponential type, dual-branches with sophisticated gate and substrate control for lower voltage operation. Published charge pumps are grouped based on architecture, operation principles and pump optimization techniques with their pros and cons compared and results contrasted. The various charge pump topologies and schemes used are considered based on pumping efficiency, power efficiency, charge transferability, circuit complexity, pumping capacitors, form factor and minimum supply voltages with an optimum load. This article concludes with an overview of suitable techniques and recommendations that will aid a designer in selecting the most suitable charge pump topology especially for low ambient micro energy harvesting applications.

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Section: Bootstrap Charge Pumpmentioning

confidence: 99%

Review of Charge Pump Topologies for Micro Energy Harvesting Systems

Mi¹,

Islam

Sampe

et al. 2016

American Journal of Applied Sciences

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show abstract

“…Since MN 3 is off at time T1, the charge on N 3 (a) The Clock Generator in the proposed Clock Driver has delay cells that generate 4 phase clocks, so that the charge transfer in the reverse direction between adjacent stages can be blocked, during transition in each clock. The proposed Clock Generator produces 4-phase clocks, by adding only delay to each clock, and the structure is simple, against the previous complicated 4-phase clock generators [9][10][11][12]16]. Fig.…”

Section: Building Blocksmentioning

confidence: 99%

“…2 Additionally, since these switches will have small parasitic capacitance and resistance, they will have minimal impact on the charge pump operation, and additional area will not be needed, in terms of chip area. The charge pump core proposed in this paper does not suffer from voltage drop due to the threshold voltage, body-effect and gate oxide breakdown, as compared to the conventional Dickson charge pump [6][7][8][9][10][11][12][13][14].…”

Section: Reconfigurable Charge Pump Architecturementioning

confidence: 99%

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A Wide Output Range, High Power Efficiency Reconfigurable Charge Pump in 0.18 mm BCD process

Park¹,

Jang²,

Cho³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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“…Using auxiliary MOSFETs to control the body terminals may also generate the substrate current [6]. Four-phase charge pump circuits were proposed, but they must have complex clock generators [7]. Wu and Chang proposed the charge pump circuit that use charge transfer switches (CTS's) to transfer charges without the limitation of threshold voltage [8].…”

Section: Introductionmentioning

confidence: 99%

A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage processes

Ker

Chen

Tsai

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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Charge Pump Circuits have been widely used in DRAM, EEPROM, flash memories, and in some low-voltage designs. In this paper, a new charge pump circuit is proposed. The charge transfer switches of the new proposed circuit can be turned on and turned off completely, so its pumping gain is much higher than the traditional designs. Besides, there is no gate-oxide reliability problem in the proposed charge pump circuit. The test chips have been implemented in a 3.3 V 0.35 µm CMOS process. The measured results show that the proposed charge pump circuit has better performance than that of prior arts. The proposed circuit can be used in low-voltage process because of its high pumping gain and no overstress across the gate oxide of the devices.

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A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation

Cited by 42 publications

References 12 publications

Review of Charge Pump Topologies for Micro Energy Harvesting Systems

Review of Charge Pump Topologies for Micro Energy Harvesting Systems

A Wide Output Range, High Power Efficiency Reconfigurable Charge Pump in 0.18 mm BCD process

A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage processes

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