A 16-bit resistor string dac with full-calibration at final test

Parthasarathy, K.L.; Kuyel, T.; Yu, Zhongjun; Chen, Degang; Geiger, R.L.

doi:10.1109/test.2005.1583962

Cited by 14 publications

(4 citation statements)

References 3 publications

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“…In the first case INL values are assumed to be uniformly distributed in the interval (− 1 /3, 1 /3) assuming N = 200, 500. In the second case a resistor-ladder based ADC is simulated, assuming resistances drawn from a Gaussian distribution with coefficient of variation of 15% [19]. This architecture guarantees monotonicity of the quantizer while allowing for rather large values of INL.…”

Section: Effect Of Quantizer Nonlinearitymentioning

confidence: 99%

Information and Statistical Efficiency When Quantizing Noisy DC Values

Moschitta

Schoukens

Carbone

2015

IEEE Trans. Instrum. Meas.

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This paper considers estimation of a quantized constant in noise when using uniform and nonuniform quantizers. Estimators based on simple arithmetic averages, on sample statistical moments and on the maximum-likelihood procedure are considered. It provides expressions for the statistical efficiency of the arithmetic mean by comparing its variance to the proper Cramér-Rao lower bound. It is conjectured that the arithmetic mean is optimal among all estimators with an exactly known bias. Conditions under which its statistical performance are improved by the other estimation procedures when the exact bias is not known are found and analyzed. Using simulations and analysis of experimental data, it is shown that both momentbased and maximum-likelihood-based estimators provide better results, when the noise standard deviation is comparable with the quantization step and the noise model of quantization can not be applied.Index Terms-Cramér-Rao lower bound (CRLB), estimation, nonlinear quantizers, quantization.

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Section: Effect Of Quantizer Nonlinearitymentioning

confidence: 99%

Information and Statistical Efficiency When Quantizing Noisy DC Values

Moschitta

Schoukens

Carbone

2015

IEEE Trans. Instrum. Meas.

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“…Therefore, its performance is highly relay on the design of its digital to analogous converter (DAC). There are many types of DAC structures that have been proposed in the literature [5][6][7][8][9][10][11][12]. Resistor based DAC architecture is one of the most attractive due to its simplicity structure, high stability, high monotonic, and low power consumption [12] and is a good choice for space application.…”

Section: Introductionmentioning

confidence: 99%

“…It also faces the increasing of instability due to the effectiveness of processing technology on the larger number of resistors. In order to solve such problems, the researchers have developed many types of architecture such as subranging [5], dual-ladder resistor [6], resistor-floatingresistor-string [7], embedded operational amplifier [8], and multibits calibration [9]. Nonetheless, all those methods are able to improve some the DAC circuit in different ways; there are still more space that can be improved, especially in the application of space environment.…”

Section: Introductionmentioning

confidence: 99%

A New Digital to Analog Converter Based on Low-Offset Bandgap Reference

Qiu

Liu

Chen

et al. 2017

Journal of Electrical and Computer Engineering

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This paper presents a new 12-bit digital to analog converter (DAC) circuit based on a low-offset bandgap reference (BGR) circuit with two cascade transistor structure and two self-contained feedback low-offset operational amplifiers to reduce the effects of offset operational amplifier voltage effect on the reference voltage, PMOS current-mirror mismatch, and its channel modulation. A Start-Up circuit with self-bias current architecture and multipoint voltage monitoring is employed to keep the BGR circuit working properly. Finally, a dual-resistor ladder DAC-Core circuit is used to generate an accuracy DAC output signal to the buffer operational amplifier. The proposed circuit was fabricated in CSMC 0.5 μm 5 V 1P4M process. The measured differential nonlinearity (DNL) of the output voltages is less than 0.45 LSB and integral nonlinearity (INL) less than 1.5 LSB at room temperature, consuming only 3.5 mW from a 5 V supply voltage. The DNL and INL at −55°C and 125°C are presented as well together with the discussion of possibility of improving the DNL and INL accuracy in future design.

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“…However, the differences between the opamp offset voltages may result in even larger mismatch current. In [7], a fuse array is utilized to adjust the DAC INL during the final test. While guaranteeing the final resolution, it requires large area for the fuse array and an accurate external tester, which raises the test cost.…”

Section: Introductionmentioning

confidence: 99%

A self-testing and calibration technique for current-steering DACs

Huang

2008

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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In this paper, a current-steering DAC self-testing and calibration technique is proposed. In the proposed scheme, the lower bits of the DAC are duplicated and an analog comparator is added to facilitate self-testing and calibration. In selftesting mode, the controller executes the self-testing algorithm to characterize the DAC higher bits and computes the calibration information. In function mode, it produces the inputs to the duplicated lower bits for calibration. To validate the idea, a 14-bit prototype has been fabricated using TSMC 0.35 µm technology. The measurement results show that INL, DNL, and SFDR are significantly improved.

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A 16-bit resistor string dac with full-calibration at final test

Cited by 14 publications

References 3 publications

Information and Statistical Efficiency When Quantizing Noisy DC Values

Information and Statistical Efficiency When Quantizing Noisy DC Values

A New Digital to Analog Converter Based on Low-Offset Bandgap Reference

A self-testing and calibration technique for current-steering DACs

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