A 16 bit low-power-consumption digital signal processor using a 80 MOPS redundant binary MAC

This paper describes a 16-bit fiied point digital signal processor (DSP), which is targeted for telecommunication applications such as modems or low-bitrate speech CODECs. A variable pipeline multiplieraccumulator (MAC) unit and several additional circuits such as a dual-purpose shift register are used to improve performance per MIPS. The DSP chip is fabricated with 0 5 pm CMOS process and achieves 40 MIPS and 80 MOPS-peak performance at 3.0V. PSI-CELP (Pitch Synchronous Innovation Code Excited Linear Prediction) speech CODEC can be implemented on this DSP with enough margin.

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A 16 bit low-power-consumption digital signal processor using a 80 MOPS redundant binary MAC

Cited by 3 publications

References 3 publications

An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor

An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor

A 1.8 V 36 mW DSP for the half-rate speech codec

A 16 bit low-power-consumption digital signal processor for portable terminals

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