An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor

Kabuo, H.; Okamoto, Michio; Tanaka, I.; Yasoshima, H.; Marui, S.; Yamasaki, Masayuki; Sugimura, Toshio; Ueda, Katsuhiko; Ishikawa, Takashi; Suzuki, Hiroyoshi; Asahi, R.

doi:10.1109/4.499725

Cited by 14 publications

(4 citation statements)

References 5 publications

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“…In cellular phone communications, transistors are mostly used in logic circuits, which may work at a low clock frequency. The earliest mobile phone processors were typically clocked at a few megahertz 9 . However, the front-end rectifiers must always operate at the transmission microwave frequencies: 935 MHz to 1.88 GHz for cellular communications, around 2.4 GHz for typical IEEE 802.11b/g/n Wi-Fi channels and Bluetooth, 1.58542 and 1.2276 GHz for global satellite positioning, 3.8 GHz for highest 4G long-term evolution (LTE) band and even 5 GHz for the newest 802.11a/h/j/n/ac Wi-Fi channels.…”

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confidence: 99%

Flexible indium–gallium–zinc–oxide Schottky diode operating beyond 2.45 GHz

et al. 2015

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Mechanically flexible mobile phones have been long anticipated due to the rapid development of thin-film electronics in the last couple of decades. However, to date, no such phone has been developed, largely due to a lack of flexible electronic components that are fast enough for the required wireless communications, in particular the speed-demanding front-end rectifiers. Here Schottky diodes based on amorphous indium-gallium-zinc-oxide (IGZO) are fabricated on flexible plastic substrates. Using suitable radio-frequency mesa structures, a range of IGZO thicknesses and diode sizes have been studied. The results have revealed an unexpected dependence of the diode speed on the IGZO thickness. The findings enable the best optimized flexible diodes to reach 6.3 GHz at zero bias, which is beyond the critical benchmark speed of 2.45 GHz to satisfy the principal frequency bands of smart phones such as those for cellular communication, Bluetooth, Wi-Fi and global satellite positioning.

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confidence: 99%

Flexible indium–gallium–zinc–oxide Schottky diode operating beyond 2.45 GHz

et al. 2015

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“…A similar approach is used in [9]. Instead of two multipliers, only one multiplier working at double the frequency, is used.…”

Section: Figure 3: Lucent Dsp16210 Architecturementioning

confidence: 99%

“…The Texas Instruments TMS320C54x and the processors described in [9] use a different approach which also results in 4 cycles per butterfly. This is illustrated in Figure 7.…”

Section: Figure 5: Viterbi Butterflymentioning

confidence: 99%

Low power DSP's for wireless communications (embedded tutorial session)

Verbauwhede

Nicol²

2000

Proceedings of the 2000 International Symposium on Low Power Electronics and Design - ISLPED '00

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Wireless communications and more specifically, the fast growing penetration of cellular phones and cellular infrastructure are the major drivers for the development of new programmable Digital Signal Processors (DSP's). In this tutorial, an overview will be given of recent developments in DSP processor architectures, that makes them well suited to execute computationally intensive algorithms typically found in communications systems. DSP processors have adapted instruction sets, memory architectures and data paths to execute compute intensive communications algorithms efficiently and in a low power fashion. Basic building blocks include convolutional decoders (mainly the Viterbi algorithm), turbo coding algorithms, FIR filters, speech coders, etc. This is illustrated with examples of different commercial and research processors. Please note that the authors do not endorse the processors used in this tutorial. These processors are used to illustrate how different solutions are proposed for the same problem.

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“…The DSP was fabricated with 0.5μm CMOS process. Kabuo et al [2] designed a 16-bit fixed-point DSP with optimized multiply-accumulate (MAC) unit, memories, and instruction sets, which reduced the area and power consumption significantly. The DSP, which was fabricated on 0.5μm double-metal-layer CMOS process, could attain double speed MAC performance.…”

Section: Introductionmentioning

confidence: 99%

Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process

Sugii

Kamohara

et al. 2015

2015 International Conference on IC Design &Amp; Technology (ICICDT)

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In this paper, a design of 16-bit fixed-point digital signal processor (DSP) is proposed. This DSP is based on the Harvard architecture, having two buses for ALU and a pipeline multiply accumulator (MAC). It composes of 16 general purpose 24-bit registers together with 41 four-cycle instruction sets. The DSP has a simple structure which is compact and flexible. The DSP is designed for low-power consumption, and implemented on ASIC using SOTB 65nm process which is a kind of SOI devices. The DSP chip consumes very low-power consumption 282µW at the operation voltage 0.55V and operation frequency 200MHz.

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An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor

Cited by 14 publications

References 5 publications

Flexible indium–gallium–zinc–oxide Schottky diode operating beyond 2.45 GHz

Flexible indium–gallium–zinc–oxide Schottky diode operating beyond 2.45 GHz

Low power DSP's for wireless communications (embedded tutorial session)

Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process

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