Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process

Le, Duc-Hung; Sugii, Nobuyuki; Kamohara, S.; Nguyen, Xuan-Thuan; Ishibashi, Koji; Pham, Cong‐Kha

doi:10.1109/icicdt.2015.7165918

Cited by 4 publications

(1 citation statement)

References 9 publications

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“…It is also possible to achieve energy-efficiencies in the range of a couple of pJ/op. Wilson et al designed a VLIW DSP for embedded F max tracking with only 62 pJ/op at 0.53V [20], and a 16b low-power fixed-point DSP with only about 5 pJ/op has been proposed by Le et al [21]. DSPs typically have zero overhead loops to eliminate branch overheads and can execute operations in parallel, but are harder to program than general purpose processors.…”

Section: Related Workmentioning

confidence: 99%

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

Gautschi

Schiavone

Traber

et al. 2017

IEEE Trans. VLSI Syst.

347

270

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Endpoint devices for Internet-of-Things not only need to work under extremely tight power envelope of a few milliwatts, but also need to be flexible in their computing capabilities, from a few kOPS to GOPS. Near-threshold (NT) operation can achieve higher energy efficiency, and the performance scalability can be gained through parallelism. In this paper we describe the design of an opensource RISC-V processor core specifically designed for NT operation in tightly coupled multi-core clusters. We introduce instructionextensions and microarchitectural optimizations to increase the computational density and to minimize the pressure towards the shared memory hierarchy. For typical data-intensive sensor processing workloads the proposed core is on average 3.5× faster and 3.2× more energy-efficient, thanks to a smart L0 buffer to reduce cache access contentions and support for compressed instructions. SIMD extensions, such as dot-products, and a built-in L0 storage further reduce the shared memory accesses by 8× reducing contentions by 3.2×. With four NT-optimized cores, the cluster is operational from 0.6 V to 1.2 V achieving a peak efficiency of 67 MOPS/mW in a low-cost 65 nm bulk CMOS technology. In a low power 28 nm FDSOI process a peak efficiency of 193 MOPS/mW (40 MHz, 1 mW) can be achieved.Index Terms-Internet-of-Things, Ultra-low-power, Multi-core, RISC-V, ISA-extensions.

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Section: Related Workmentioning

confidence: 99%