A 16 bit low-power-consumption digital signal processor for portable terminals

Ishikawa, Takashi; Suzuki, Hiroyoshi; Taki, Hirokazu; Homma, Koichi; Kabuo, H.; Okamoto, Michio; Ueda, Katsuhiko; Asahi, R.

doi:10.1109/icupc.1995.497119

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“…Ishikawa et al [1] described a 16-bit fixed-point DSP for telecommunication applications. The DSP was fabricated with 0.5μm CMOS process.…”

Section: Introductionmentioning

confidence: 99%

Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process

Sugii

Kamohara

et al. 2015

2015 International Conference on IC Design &Amp; Technology (ICICDT)

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In this paper, a design of 16-bit fixed-point digital signal processor (DSP) is proposed. This DSP is based on the Harvard architecture, having two buses for ALU and a pipeline multiply accumulator (MAC). It composes of 16 general purpose 24-bit registers together with 41 four-cycle instruction sets. The DSP has a simple structure which is compact and flexible. The DSP is designed for low-power consumption, and implemented on ASIC using SOTB 65nm process which is a kind of SOI devices. The DSP chip consumes very low-power consumption 282µW at the operation voltage 0.55V and operation frequency 200MHz.

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“…Ishikawa et al [1] described a 16-bit fixed-point DSP for telecommunication applications. The DSP was fabricated with 0.5μm CMOS process.…”

Section: Introductionmentioning

confidence: 99%