A 16 b low-power-consumption digital signal processor

Ueda, Katsuhiko; Sugimura, Toshio; Okamoto, Michio; Marui, S.; Ishikawa, Takashi; Sakakihara, Mikio

doi:10.1109/isscc.1993.280098

Cited by 12 publications

(4 citation statements)

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“…The reason is that only small on-chip memories can be accessed in a single clock cycle. This problem is addressed in [4]. The multiply-accumulate unit operates at double the clock frequency compared to the memory accesses.…”

Section: Alternative Approachesmentioning

confidence: 99%

Low power DSP engine for wireless communications

Verbauwhede¹,

Touriguian²

1999

Computer Standards & Interfaces

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Section: Alternative Approachesmentioning

confidence: 99%

Low power DSP engine for wireless communications

Verbauwhede¹,

Touriguian²

1999

Computer Standards & Interfaces

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“…The multiplier-accumulator executes the following operation C = A X B + C (1) where A is the m-bit multiplier, B is the n-bit multiplicand, and C is the x-bit accumulated number which is stored once in the register and then fed back (x > m + n). Usually, the multiplier-accumulator is composed of the multiplier and the parallel adder.…”

Section: Construction Of Multiplier-accumulatormentioning

confidence: 99%

A high‐speed high‐density array‐multiplier‐accumulator for digital signal processing

Minami

Kasai

Matsuda

et al. 1996

Electron Comm Jpn Pt II

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This paper discusses the downsizing and speed improvement of short-word multiplier-accumulators, which are frequently used in digital signal processors. As a first step, the optimal configuration for an array-type carry-save adder is considered where the shortest path in the full-adder is used to propagate the sum signal and the carry signal is sent to the full-adder of the two lower stages by skipping a stage. A configuration of the fulladder suitable for the structure is proposed. The case of eight partial product additions shows that the delay can be reduced by 22 percent compared to a simple arraytype carry-save adder. Then the short-word carry lookahead adder using the pass-transistor logic is considered. It is shown that a single-stage carry look-ahead circuit with a four-bitwise iterative structure exhibits nearly the same delay as a two-stage carry look-ahead circuit. In other words, the former is better suited to downsizing. This paper intends to examine the effectiveness of the foregoing new array-type carry-save adder and the single-stage carry look-ahead circuit using the 0.5-pm CMOS technology. A 16-bit x 1Cbit + 31-bit multiplieraccumulator has been designed and is evaluated for cases where the array-type carry-save adder is used to handle accumulation as well as partial products. The resulting area and delay are 0.77 x 0.78 m2 and 6.8 ns, respectively. The effectiveness of the approach used in this paper is evaluated by constructing a multiplier-accumulator, but the method is also useful in constructing a multiplier.

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“…Programmable DSPs were extensively specialized for digital cellular phones [21,22], and the development of cable modems and DSL modems created several new types of dedicated communications DSPs [23]. Gigabit Ethernet and broadband wireless likewise required dedicated DSP hardware [24].…”

Section: The More-recent Eramentioning

confidence: 99%

50 years of signal processing at ISSCC

Thon¹

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.

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The FieldThe technical field of Signal Processing encompasses all forms of sampled-data manipulation where the data (or signal) has a physical origin, or destination. In the context of ISSCC, signal processing refers to solid-state circuits designed to process samples that may be in digital or analog format. Physical origins or destinations include mechanical (audio) and electromagnetic waves (either in conductors or in free space), such as for telephony, radio, imaging, or optical transmission.The restriction to sampled data is an important one, and distinguishes signal processing from purely continous-time processing, as is performed by traditional analog circuits. While discrete time (or space) is of the essence, what characterizes signal processing at ISSCC is also the continuous real-time nature of the processing, as opposed to the matched process of data collection followed by off-line processing. The Early YearsDefinitions aside, signal processing has a long and distinguished history at the Conference. However, the pace of development has definitely quickened in the last 25 years. An early example of sampled-data (analog) processing was presented by Franks in 1960 [1], in a paper describing a sampled-data bandpass filtering process based on junction-diode switching.Development of signal-processing circuits began to accelerate in the 1970s. Significant milestones in analog and digital sampled-data-processing are exemplified by the papers on CCD circuits [2], and the first integrated digital filter [3]. The sampledanalog CCD technique was used in what was perhaps the first dedicated implementation of the Discrete Fourier Transform [4]. The most significant advantage of CCD and switched-capacitor [5] circuits was that no analog-todigital conversion was needed for the signals. However, the increased effort required to obtain a robust design of ever-morecomplex analog sampled-data circuits resulted in a market opportunity for digital solutions.Simultaneous progress in the area of A/D and D/A data-conversion circuits permitted the use of highly-integrated digital signal-processing functions in an economical manner. In particular, the early 1980s saw the first examples of programmable DSP circuits [6,7,8]. The VLSI era also introduced the first examples of complex hard-wired or dedicated DSP functions [9] on a chip. With increasingly-complex numerical algorithms, ease of programming was provided by DSPs that used floating-point rather than fixed-point instruction sets [10]. The More-Recent EraSince the mid 1980s, both analog and digital signal processing were strongly affected by a change from NMOS and bipolar/BiMOS to CMOS technology. This allowed a succession of new application areas, such as speech synthesis and coding/decoding [11,12,13], speech recognition [14], and image processing [15,16,17]. At the same time, although more slowly, "digital" CMOS was being adopted for the fabrication of analog signal-processing functions.By exploiting the progress of CMOS developed for microprocessors, digital signal proce...

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A 16 b low-power-consumption digital signal processor

Cited by 12 publications

References 0 publications

Low power DSP engine for wireless communications

Low power DSP engine for wireless communications

A high‐speed high‐density array‐multiplier‐accumulator for digital signal processing

50 years of signal processing at ISSCC

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