A high‐speed high‐density array‐multiplier‐accumulator for digital signal processing

Abstract

This paper discusses the downsizing and speed improvement of short-word multiplier-accumulators, which are frequently used in digital signal processors. As a first step, the optimal configuration for an array-type carry-save adder is considered where the shortest path in the full-adder is used to propagate the sum signal and the carry signal is sent to the full-adder of the two lower stages by skipping a stage. A configuration of the fulladder suitable for the structure is proposed. The case of eight partial product additions shows that the delay can be reduced by 22 percent compared to a simple arraytype carry-save adder. Then the short-word carry lookahead adder using the pass-transistor logic is considered. It is shown that a single-stage carry look-ahead circuit with a four-bitwise iterative structure exhibits nearly the same delay as a two-stage carry look-ahead circuit. In other words, the former is better suited to downsizing. This paper intends to examine the effectiveness of the foregoing new array-type carry-save adder and the single-stage carry look-ahead circuit using the 0.5-pm CMOS technology. A 16-bit x 1Cbit + 31-bit multiplieraccumulator has been designed and is evaluated for cases where the array-type carry-save adder is used to handle accumulation as well as partial products. The resulting area and delay are 0.77 x 0.78 m2 and 6.8 ns, respectively. The effectiveness of the approach used in this paper is evaluated by constructing a multiplier-accumulator, but the method is also useful in constructing a multiplier.