A 151mm&lt;sup&gt;2&lt;/sup&gt; 64Gb MLC NAND flash memory in 24nm CMOS technology

Fukuda, Koichi; Watanabe, Yoshihisa; Makino, Eiichi; Kawakami, Koichi; Sato, Jumpei; Takagiwa, Teruo; Kanagawa, Naoaki; Shiga, H.; Tokiwa, N.; Shindo, Yoshitaro; Toshiaki, Edahiro; Ogawa, Takahisa; Iwai, M.; Nagao, Osamu; Musha, Junji; Minamoto, Takatoshi; Yanagidaira, Kosuke; Suzuki, Yuya; Nakamura, Dai; Hosomura, Yoshikazu; Komai, Hiromitsu; Furuta, Yuichi; Muramoto, Mai; Tanaka, R.; Shikata, G.; Yuminaka, A.; Sakurai, Kazuo; Sakai, Manabu; Ding, Hong; Watanabe, Mitsuyuki; Kato, Yasuyuki; Miwa, Takaki; Mak, Alex; Nakamichi, M.; Hemink, G.; Lee, Dana; Higashitani, M.; Murphy, Brian J.; Lei, Bo; Matsunaga, Y.; Naruke, K.; Hara, T.

doi:10.1109/isscc.2011.5746280

Cited by 6 publications

(3 citation statements)

References 2 publications

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“…The average set/reset time including verification is 138 and 70 ns, respectively, which is 10000 times shorter than that of the NAND flash memory. 13) As shown in Fig. 10(f ), the worn LRS could be recovered by the long width set pulses.…”

Section: Incremental Voltage With Turnback Setmentioning

confidence: 81%

Endurance Enhancement and High Speed Set/Reset of 50 nm Generation HfO₂ Based Resistive Random Access Memory Cell by Intelligent Set/Reset Pulse Shape Optimization and Verify Scheme

Higuchi¹,

Miyaji²,

Koh³

et al. 2012

Jpn. J. Appl. Phys.

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This paper proposes a verify-programming method for the resistive random access memory (ReRAM) cell which achieves a 50-times higher endurance and a fast set and reset compared with the conventional method. The proposed verify-programming method uses the incremental pulse width with turnback (IPWWT) for the reset and the incremental voltage with turnback (IVWT) for the set. With the combination of IPWWT reset and IVWT set, the endurance-cycle increases from 48 ×103 to 2444 ×103 cycles. Furthermore, the measured data retention-time after 20 ×103 set/reset cycles is estimated to be 10 years. Additionally, the filamentary based physical model is proposed to explain the set/reset failure mechanism with various set/reset pulse shapes. The reset pulse width and set voltage correspond to the width and length of the conductive-filament, respectively. Consequently, since the proposed IPWWT and IVWT recover set and reset failures of ReRAM cells, the endurance-cycles are improved.

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Section: Incremental Voltage With Turnback Setmentioning

confidence: 81%

Endurance Enhancement and High Speed Set/Reset of 50 nm Generation HfO₂ Based Resistive Random Access Memory Cell by Intelligent Set/Reset Pulse Shape Optimization and Verify Scheme

Higuchi¹,

Miyaji²,

Koh³

et al. 2012

Jpn. J. Appl. Phys.

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“…The NAND flash memories in solid-state drives (SSDs) are continuously scaled down to realize the high storage capacity and low-cost [3]. Recently, the feature size of NAND flash memories has reached 16nm [4].…”

Section: Introductionmentioning

confidence: 99%

A scaling scenario of asymmetric coding to reduce both data retention and program disturbance of NAND flash memories

Doi

Tanakamaru

Takeuchi

2014

Solid-State Electronics

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An optimized asymmetric coding strategy is proposed to improve the reliability of the NAND flash memories. The previously reported asymmetric coding reduces the dataretention error by decreasing the population of the V TH state which has higher error rate, and is measured on 4Xnm NAND flash memory [1]. In [2], by increasing the number of the lowest V TH state, the proposed asymmetric coding strategy reduces the V PGM disturbance, and alleviates the floating-gate (FG)-FG coupling. And also, the program-disturb bit error rates (BERs) in 2Xnm, 3Xnm, and 4Xnm NAND flash memories are reduced by 71%, 73%, and 89%, respectively. In this paper, the effect of asymmetric coding on the data-retention error is investigated in 2Xnm NAND flash memory. From the measured results, the proposed asymmetric coding effectively increases the population of the lowest V TH state which has no data-retention error. The data-retention BERs in 2Xnm, 3Xnm and 4Xnm NAND are decreased by 17%, 52% and 70%, respectively.Keywords: NAND flash memory, asymmetric coding, reliability, program disturb error, dataretention error M. Doi et al., " A Scaling Scenario of Asymmetric Coding to Reduce Both Data Retention and Program Disturbance of NAND Flash Memories" 3 / 15 I.

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“…1. The mainstream solution for NVM integration is FLASH technology [11], [12]. Emerging NVMs typically include resistive RAMs (R-RAM) [13], magnetic RAMs (M-RAM) [14], phase-change RAMs (PC-RAM) [15], conductive-bridge RAMs (CB-RAM) [16], and ferroelectric RAMs (Fe-RAM) [17].…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of anchorless shuttle nano-electro-mechanical non-volatile memory for high temperature applications

Vaddi

Kim

Pott

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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A 151mm<sup>2</sup> 64Gb MLC NAND flash memory in 24nm CMOS technology

Cited by 6 publications

References 2 publications

Endurance Enhancement and High Speed Set/Reset of 50 nm Generation HfO₂ Based Resistive Random Access Memory Cell by Intelligent Set/Reset Pulse Shape Optimization and Verify Scheme

Endurance Enhancement and High Speed Set/Reset of 50 nm Generation HfO₂ Based Resistive Random Access Memory Cell by Intelligent Set/Reset Pulse Shape Optimization and Verify Scheme

A scaling scenario of asymmetric coding to reduce both data retention and program disturbance of NAND flash memories

Design and analysis of anchorless shuttle nano-electro-mechanical non-volatile memory for high temperature applications

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A 151mm<sup>2</sup> 64Gb MLC NAND flash memory in 24nm CMOS technology

Cited by 6 publications

References 2 publications

Endurance Enhancement and High Speed Set/Reset of 50 nm Generation HfO2 Based Resistive Random Access Memory Cell by Intelligent Set/Reset Pulse Shape Optimization and Verify Scheme

Endurance Enhancement and High Speed Set/Reset of 50 nm Generation HfO2 Based Resistive Random Access Memory Cell by Intelligent Set/Reset Pulse Shape Optimization and Verify Scheme

A scaling scenario of asymmetric coding to reduce both data retention and program disturbance of NAND flash memories

Design and analysis of anchorless shuttle nano-electro-mechanical non-volatile memory for high temperature applications

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Product

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Endurance Enhancement and High Speed Set/Reset of 50 nm Generation HfO₂ Based Resistive Random Access Memory Cell by Intelligent Set/Reset Pulse Shape Optimization and Verify Scheme

Endurance Enhancement and High Speed Set/Reset of 50 nm Generation HfO₂ Based Resistive Random Access Memory Cell by Intelligent Set/Reset Pulse Shape Optimization and Verify Scheme