A 151-mm$^{2}$ 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology

Fukuda, Koichi; Watanabe, Yoshihiro; Makino, Eiichi; Kawakami, Koichi; Sato, Jumpei; Takagiwa, Teruo; Kanagawa, Naoaki; Shiga, H.; Tokiwa, N.; Shindo, Yoshitaro; Ogawa, Takahisa; Toshiaki, Edahiro; Iwai, M.; Nagao, Osamu; Musha, Junji; Minamoto, Takatoshi; Furuta, Yuichi; Yanagidaira, Kosuke; Suzuki, Y.; Nakamura, Dai; Hosomura, Yoshikazu; Tanaka, R.; Komai, Hiromitsu; Muramoto, Mai; Shikata, G.; Yuminaka, A.; Sakurai, Kazuo; Sakai, Manabu; Ding, Hong; Watanabe, Makoto; Kato, Yasuyuki; Miwa, Takaki; Mak, Alex; Nakamichi, M.; Hemink, G.; Lee, D.; Higashitani, M.; Murphy, Brian J.; Lei, Bo; Matsunaga, Y.; Naruke, K.; Hara, T.

doi:10.1109/jssc.2011.2164711

Cited by 10 publications

(14 citation statements)

References 7 publications

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“…18. With the most scaled 15 nm technology and an optimized floor plan of peripheral circuits [3], the die size of 75 mm , which is smaller than the previously reported 64 Gb MLC NAND flash memory [5], is achieved. The die can fit in 10 11 BGA package, which is suitable for mobile applications.…”

Section: Key Chip Featuresmentioning

confidence: 95%

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A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology

Sako

Watanabe

Nakajima

et al. 2016

IEEE J. Solid-State Circuits

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A 75 mm low power 64 Gb MLC NAND flash memory capable of 30 MB/s program throughput and 533 MB/s data transfer rate at 1.8 V supply voltage is developed in 15 nm CMOS technology. 36% power reduction from 3.3 V design is achieved by a new pumping scheme. New low current peak features reduce a multi-die concurrent programming peak by 65% for 4-die case, and an erase verifying peak by 40%, respectively. Nanoscale transistors reducing bit-line discharge time by 70% is introduced to improve performance.Index Terms-NAND flash memory, low power, low peak current, nanoscale transistor, peak power management, smart pumping power control, 15 nm.Mario Sako was born in Gifu, Japan, in 1979. He received the B.E. degree in electronic engineering from Nagoya Institute of Technology and M.E. degree in electronic engineering from Nagoya University, Aichi, Japan, in 2003 and 2005, respectively. In 2005, he joined the Memory Design Department, Toshiba Corporation, Yokohama, Japan. Since 2008, he has been working on the circuit design of NAND flash memories.

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Section: Key Chip Featuresmentioning

confidence: 95%

“…Therefore, the sense amplifier for low needs a boosted voltage. A row decoder [3] for low is shown in Fig. 6.…”

Section: Power Reductionmentioning

confidence: 99%

A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology

Sako

Watanabe

Nakajima

et al. 2016

IEEE J. Solid-State Circuits

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“…In NAND flash memories, various techniques for reducing peak ICC have been proposed [1]- [6]. In [1], a selective BL pre-charge, source-line program, and an intelligent interleaving scheme are proposed.…”

Section: Related Technologiesmentioning

confidence: 99%

“…In [2], the drivability control of a BL pre-charge driver by reference voltage and bias slope are addressed. An adaptive code selection scheme and a smart pre-charge algorithm are also introduced in [5] and [6], respectively. In [4], the sequential sensing concept is addressed, which enables a BL to pre-charge only once in a multilevel sensing.…”

Section: Related Technologiesmentioning

confidence: 99%

“…Many previous research ideas have focused on suppressing peak ICC [1]- [6]; however, one of the difficulties encountered with these approaches is that the cache program operation is not seriously considered. However, since the target biasing of the write operation is much higher than that of the read operation, the peak current consumption (peak ICC) during the programming operation is becoming one of the largest concerns in low-power NAND flash memory design.…”

Section: Introductionmentioning

confidence: 99%

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Program Cache Busy Time Control Method for Reducing Peak Current Consumption of NAND Flash Memory in SSD Applications

Park

Kim

Cho

et al. 2014

ETRI J

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In current NAND flash design, one of the most challenging issues is reducing peak current consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in NAND flash memory. This paper presents an efficient approach for reducing the peak ICC of the cache program in NAND flash memory — namely, a program Cache Busy Time (tPCBSY) control method. The proposed tPCBSY control method is based on the interesting observation that the array program current (ICC2) is mainly decided by the bit‐line bias condition. In the proposed approach, when peak ICC2 becomes larger than a threshold value, which is determined by a cache loop number, cache data cannot be loaded to the cache buffer (CB). On the other hand, when peak ICC2 is smaller than the threshold level, cache data can be loaded to the CB. As a result, the peak ICC of the cache program is reduced by 32% at the least significant bit page and by 15% at the most significant bit page. In addition, the program throughput reaches 20 MB/s in multiplane cache program operation, without restrictions caused by a drop in peak power due to cache program operations in a solid‐state drive.

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