Memory Driven Design Methodologies for Optimal SSD Performance

Zuolo, Lorenzo; Zambelli, Cristian; Micheloni, Rino; Olivo, P.

doi:10.1007/978-981-13-0599-3_7

Cited by 6 publications

(6 citation statements)

References 21 publications

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“…1 shows the typical architecture of an SSD controller. The SSD controller manages the NAND flash memory and handles I/O requests received from the host [7,13]. The flash memory is spread across multiple flash chips, where each chip contains one or more flash dies.…”

Section: Ssd Controllermentioning

confidence: 99%

“…The recent explosion of information has spawned semiconductor technologies that help to store large amounts of data with a high degree of reliability and high performance at a lower cost with ever smaller form factors. Due to several advantages, including markedly faster read/write speeds, lower power consumption, and no noise, solid-state drivers (SSDs) have become the technology of choice to replace traditional hard disk drives (HDDs) [1,2,3,4,5,6]. An SSD consists of a controller ASIC (Application Specific Integrated Circuit) and a group of flash memory chips.…”

Section: Introductionmentioning

confidence: 99%

“…An SSD consists of a controller ASIC (Application Specific Integrated Circuit) and a group of flash memory chips. Usually, a data stream is stripped among these flash memory chips using multiple flash channels [7,8,9,10,11,12,13,14,15].…”

Section: Introductionmentioning

confidence: 99%

“…Controllers generally include only single-, two-or dualport SRAM. However, in an SSD controller, more than two IPs, such as the CPU, data interface, and multi-flash memory channel, simultaneously access the same SRAM [12,13]. Traditional SRAM is thus not suitable for SSD data buffers.…”

Section: Introductionmentioning

confidence: 99%

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Embedded multiport data buffer for a solid-state drive controller

Liu

Fan

Luo

et al. 2021

IEICE Electron. Express

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Solid-state drives (SSDs) for mobile and embedded systems may not provide very high performance by today's standards; however, they are small, low cost and consume little power. SSD controllers are thus designed as DRAM-less chips. SRAM cells created by the IC foundry as a standard module are embedded in the SSD controller as data buffer and can be single-port or two-port. In an SSD controller, more than two IPs simultaneously access the same SRAM, such as the CPU, data interface, and multiflash memory channel. It is thus complicated to exchange data between multiple ports. A new architecture of the multi-port data buffer (M-Buffer) is proposed in this study to solve this problem. M-Buffer is composed of wide SRAM, a smart arbitrator and several interface port logics. The M-Buffer can be designed as a reusable architecture and is small, low cost and consumes little power.

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Section: Ssd Controllermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Embedded multiport data buffer for a solid-state drive controller

Liu

Fan

Luo

et al. 2021

IEICE Electron. Express

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show abstract

“…Additionally, RAM can access data on a byte-addressable level. There are a lot of studies to improve I/O performance with RAM memory, and most of them use RAM memory as a buffer for storage devices [5][6][7][8][9]. The read and write buffer can reduce write latency by buffering incoming data to a RAM buffer, or reduce read latency to get data directly from a RAM buffer, with appropriate buffer-management algorithms.…”

Section: Introductionmentioning

confidence: 99%

A Durable Hybrid RAM Disk with a Rapid Resilience for Sustainable IoT Devices

Baek

Park

2020

Sensors

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Flash-based storage is considered to be a de facto storage module for sustainable Internet of things (IoT) platforms under a harsh environment due to its relatively fast speed and operational stability compared to disk storage. Although their performance is considerably faster than disk-based mechanical storage devices, the read and write latency still could not catch up with that of Random-access memory (RAM). Therefore, RAM could be used as storage devices or systems for time-critical IoT applications. Despite such advantages of RAM, a RAM-based storage system has limitations in its use for sustainable IoT devices due to its nature of volatile storage. As a remedy to this problem, this paper presents a durable hybrid RAM disk enhanced with a new read interface. The proposed durable hybrid RAM disk is designed for sustainable IoT devices that require not only high read/write performance but also data durability. It includes two performance improvement schemes: rapid resilience with a fast initialization and direct byte read (DBR). The rapid resilience with a fast initialization shortens the long booting time required to initialize the durable hybrid RAM disk. The new read interface, DBR, enables the durable hybrid RAM disk to bypass the disk cache, which is an overhead in RAM-based storages. DBR performs byte–range I/O, whereas direct I/O requires block-range I/O; therefore, it provides a more efficient interface than direct I/O. The presented schemes and device were implemented in the Linux kernel. Experimental evaluations were performed using various benchmarks at the block level till the file level. In workloads where reads and writes were mixed, the durable hybrid RAM disk showed 15 times better performance than that of Solid-state drive (SSD) itself.

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Adaptive Management With Request Granularity for DRAM Cache Inside nand-Based SSDs

Lin

Sha

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Memory Driven Design Methodologies for Optimal SSD Performance

Cited by 6 publications

References 21 publications

Embedded multiport data buffer for a solid-state drive controller

Embedded multiport data buffer for a solid-state drive controller

A Durable Hybrid RAM Disk with a Rapid Resilience for Sustainable IoT Devices

Adaptive Management With Request Granularity for DRAM Cache Inside nand-Based SSDs

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