A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology

Abstract

A 75 mm low power 64 Gb MLC NAND flash memory capable of 30 MB/s program throughput and 533 MB/s data transfer rate at 1.8 V supply voltage is developed in 15 nm CMOS technology. 36% power reduction from 3.3 V design is achieved by a new pumping scheme. New low current peak features reduce a multi-die concurrent programming peak by 65% for 4-die case, and an erase verifying peak by 40%, respectively. Nanoscale transistors reducing bit-line discharge time by 70% is introduced to improve performance.Index Terms-NAND flash memory, low power, low peak current, nanoscale transistor, peak power management, smart pumping power control, 15 nm.Mario Sako was born in Gifu, Japan, in 1979. He received the B.E. degree in electronic engineering from Nagoya Institute of Technology and M.E. degree in electronic engineering from Nagoya University, Aichi, Japan, in 2003 and 2005, respectively. In 2005, he joined the Memory Design Department, Toshiba Corporation, Yokohama, Japan. Since 2008, he has been working on the circuit design of NAND flash memories.

Study on the Performance of Superlattice-Like Thin Film V2O5/Sb in Phase Change Memory

“…3,4 However, flash memory has approached its size limits due to electrons leaking through the gate into neighboring cells in smaller cells. [5][6][7] Unlike flash memory, phase change memory (PCM) can be heated by a laser or a small current to shrink from a reversible transition between amorphous and crystalline states to a smaller battery size. 6,7 Additionally, PCM has a faster operation speed inherently and better cycle performance over tens of millions of times, vs only several thousand times for flash memory.…”