A 150 Mb/s PRML chip for magnetic disk drives

Mita, Seiichi; Ouchi, Y.; Takashi, Terumi; Sato, Naoki; Aoi, H.; Minoshima, S.; Hirai, Tatsuya; Miyasaka, H.; Shimokawa, R.; Matsuura, Tatsuji; Sawaguchi, H.; Miyazawa, S.; Hikasa, Kazuhiko

doi:10.1109/isscc.1996.488514

Cited by 21 publications

(3 citation statements)

References 4 publications

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“…Although the transpose form of an FIR filter is often preferred for high-speed, low-latency applications [23]- [25] the structure is difficult to parallelize because it needs to perform multiple multiply-and-add operations within a clock, by using a multiphase clock. On the other hand, the direct form FIR is parallelized by simply repeating the same structure with time-shifted inputs, which can be expressed as (4) From (4), it is easy to see that the filter can be parallelized by implementing with four identical blocks and time-shifted inputs, expressed as (5) For the FIR filters of the LE and M-DFE, the look-up table (LUT) based distributed arithmetic (DA) architecture is chosen for each of the parallelized blocks to reduce the latency and implement the filter with very low power consumption.…”

Section: Hardware Implementationmentioning

confidence: 99%

A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band

Park

Richards

Nikolić

2011

IEEE J. Solid-State Circuits

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Abstract-The wide unlicensed bandwidth of a 60 GHz channel presents an attractive opportunity for high data rate and low power personal area networks (PANs). The use of single-carrier modulation can yield energy-efficient transmitter and receiver implementation, but equalization of the long channel response in non-line-of-sight (NLOS) conditions presents a significant challenge. A digital equalizer for 60 GHz channels has been designed for both line of sight (LOS) and NLOS channel conditions to meet the IEEE WPAN standard. Power consumption is minimized by using a parallelized distributed arithmetic (DA) architecture. A 2 mm 2 mm test chip in 65nm CMOS implements a 6 tap feedforward and 32 tap feedback equalizer that can be configured to cancel the response of up to 72 symbols, and consumes 5.6 mW at 2 Gb/s throughput. The chip also includes a channel estimator based on a Golay correlator for setting the equalizer coefficients and estimating frequency and timing error.

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Section: Hardware Implementationmentioning

confidence: 99%

A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band

Park

Richards

Nikolić

2011

IEEE J. Solid-State Circuits

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“…Many state-of-the-art industrial detector implementations are based on the digital Viterbi detection algorithms with processing speed around 150 Mb/s or a little bit higher [2]- [4]. For the PR IV detection scheme, a digital chip [2] is able to perform MLSD operations at a data rate of 150 Mb/s in a 0.7-m BiCMOS technology. In the digital Viterbi detection algorithms, many operations such as summation, comparison, switching, and storage are required.…”

Section: Introductionmentioning

confidence: 99%

“…The optimal detection problem is to estimate the most possible input data sequence among all possible input 's based on the observed sequence The estimator selects that maximizes the conditional a posterior probability This is equal to minimize the cost function (2) or in the matrix format…”

Section: Introductionmentioning

confidence: 99%

A compact neural network for VLSI PRML detectors: scalable architecture

Chou

Sheu

Wang

1998

IEEE Trans. Circuits Syst. II

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Very large scale integration (VLSI) compact neural network architecture for maximum-likelihood detector of partial response (PR) communication receivers is presented. The compact neural network approach has many attractive advantages in achieving low power, low cost, compact chip area, and faster processing speed by its loosely coupled parallel processing nature. In this paper, the design of a state-constrained analog neural processor, and the corresponding parallel architecture to realize the PR detection algorithms and the related scalability and performance evaluation issues are described with detailed design analysis. A design example of PR IV detector have been used to demonstrate the advantages of such a scalable massive VLSI architecture. A processing rate of 265 Mb/s was achieved with SPICE simulation for a prototype PR IV detector on a silicon area of 5.14 mm 2 5.81 mm in a 1.2-m CMOS technology.An estimated processing capacity of 886 Mb/s can be achieved if the same design is scaled up to a 1.0-cm 2 silicon area for the same technology. Such promising performance potential clearly indicates that VLSI compact neural network detector can meet the needs in future high speed data communication systems at very low cost.Index Terms-Neural network, mixed-signal, parallel processing, partial response, scalable design, VLSI.

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