A 15 MHz to 600 MHz, 20 mW, 0.38 mm$^{2}$ Split-Control, Fast Coarse Locking Digital DLL in 0.13 $\mu$m CMOS

Hoyos, Sebastián; Tsang, Cheongyuen; Vanderhaegen, J.; Chiu, Yun; Aibara, Y.; Khorramabadi, H.; Nikolić, Borivoje

doi:10.1109/tvlsi.2011.2106170

Cited by 16 publications

(7 citation statements)

References 4 publications

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“…Conventional DLL‐based frequency synthesisers are occupying large area because of using capacitors in VCDL and LF [12]. Also, designing of DLL‐based frequency multiplier in high frequencies is difficult.…”

Section: Conventional Dll‐based Frequency Synthesisersmentioning

confidence: 99%

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Digital delay locked loop‐based frequency synthesiser for Digital Video Broadcasting‐Terrestrial receivers

Gholami¹,

Rahimpour²,

Ardeshir³

et al. 2014

IET Circuits, Devices & Systems

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In this study, the authors cover French very high frequency (VHF) band with a novel all-digital fast lock delayed looked loop (DLL)-based frequency synthesiser. Since this new architecture uses a digital signal processing unit instead of phasefrequency detector, charge pump and loop filter in conventional DLL therefore it shows better jitter performance, locktime and convergence speed. To obtain in-phase input and output signals in DLLs, optimisation methods are used in the proposed architecture. The proposed architecture is designed to cover channels of French VHF band by choosing number of delay cells in signal path. Simulation has been done for 22-27 delay cells and f REF = 16 MHz which can produce output frequency in range of 176-216 MHz. Locking time is approximately 0.5 μs which is equal to 8 clock cycles of reference clock. All of simulation results show superiority of the proposed structure.

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Section: Conventional Dll‐based Frequency Synthesisersmentioning

confidence: 99%

“…Usually clock multiplications circuits are designed by PLLs and DLLs [11]. Nowadays, DLLs are used more than PLLs because of faster locking process [12], lower phase noise [13], lower jitter and better stability conditions [14].…”

Section: Introductionmentioning

confidence: 99%

Digital delay locked loop‐based frequency synthesiser for Digital Video Broadcasting‐Terrestrial receivers

Gholami¹,

Rahimpour²,

Ardeshir³

et al. 2014

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

“…Conventional DLL‐based frequency synthesizers are occupying large area because of using capacitors in VCDL and LF . Also, designing DLL‐based frequency multiplier in high frequencies is difficult.…”

Section: Architecture Of Conventional Dllsmentioning

confidence: 99%

“…Usually clock multiplications circuits are designed by PLLs and DLLs . Nowadays, DLLs are used more than PLLs because of faster locking process , lower phase noise , lower jitter, and better stability conditions .…”

Section: Introductionmentioning

confidence: 99%

A new fast‐lock, low‐jitter, and all‐digital frequency synthesizer for DVB‐T receivers

Gholami

Rahimpour

Ardeshir

et al. 2013

Circuit Theory & Apps

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SUMMARYLock time and convergence time are the most important challenges in delay-locked loops (DLLs). In this paper we cover French very high frequency band with a novel all-digital fast-lock DLL-based frequency synthesizer. Because this new architecture uses a digital signal processing unit instead of using phase frequency detector, charge pump, and loop filter in conventional DLL, therefore, it shows better jitter performance, lock time, and convergence speed than previous related works. Optimization methods are used to make input and output signals of the proposed DLL in phase. The proposed architecture is designed to cover all channels of French very high frequency band by choosing number of delay cells in signal path. Simulation has been done for 22-27 delay cells, and f REF = 16 MHz, which can produce output frequency in range of 176-216 MHz. Locking time is approximately 0.3 μs, which is equal to five clock cycles of reference clock. All of the simulation results show superiority of the proposed structure.

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“…In general, the DLL is divided into analog , digital , and mixed‐mode designs . The analog DLLs employ charge pump and voltage‐controlled delay line, so they have higher accuracy and lower jitter.…”

Section: Introductionmentioning

confidence: 99%

An all‐digital DLL with duty‐cycle correction using reusable TDC

Kao

Hsieh

Cheng

2015

Circuit Theory & Apps

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This paper presents the design of an all-digital delay-locked loop (ADDLL) with duty-cycle correction using reusable time-to-digital converter (TDC). The proposed ADDLL uses a reusable TDC for achieving a wide-operating frequency range. In addition, it achieves the frequency doubling output clock easily by changing the quantization interval. It is implemented in a 0.18-μm complementary metal-oxide semiconductor technology. This circuit corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The output duty cycle is corrected to 50 ± 1.5% as the input duty cycle ranges from 25% to 75%. The acceptable input frequency range is from 300 to 900 MHz without frequency doubling. The acceptable input frequency range is from 150 to 450 MHz when using frequency doubling. It dissipates 6.2 mW from a 1.8-V supply at 900 MHz. The peak-to-peak and RMS jitters at 900 MHz are 14 and 1.8 ps, respectively.

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A 15 MHz to 600 MHz, 20 mW, 0.38 mm$^{2}$ Split-Control, Fast Coarse Locking Digital DLL in 0.13 $\mu$m CMOS

Cited by 16 publications

References 4 publications

Digital delay locked loop‐based frequency synthesiser for Digital Video Broadcasting‐Terrestrial receivers

Digital delay locked loop‐based frequency synthesiser for Digital Video Broadcasting‐Terrestrial receivers

A new fast‐lock, low‐jitter, and all‐digital frequency synthesizer for DVB‐T receivers

An all‐digital DLL with duty‐cycle correction using reusable TDC

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