An all‐digital DLL with duty‐cycle correction using reusable TDC

Abstract

This paper presents the design of an all-digital delay-locked loop (ADDLL) with duty-cycle correction using reusable time-to-digital converter (TDC). The proposed ADDLL uses a reusable TDC for achieving a wide-operating frequency range. In addition, it achieves the frequency doubling output clock easily by changing the quantization interval. It is implemented in a 0.18-μm complementary metal-oxide semiconductor technology. This circuit corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The output duty cycle is corrected to 50 ± 1.5% as the input duty cycle ranges from 25% to 75%. The acceptable input frequency range is from 300 to 900 MHz without frequency doubling. The acceptable input frequency range is from 150 to 450 MHz when using frequency doubling. It dissipates 6.2 mW from a 1.8-V supply at 900 MHz. The peak-to-peak and RMS jitters at 900 MHz are 14 and 1.8 ps, respectively.

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

“…Severe duty cycle distortion can increase the total jitter of the signal and even lead to timing errors. 32,33 A duty cycle correction circuit is needed to correct the duty cycle distortion and bring the duty cycle closer to 50%. Figure 11 shows the duty cycle correction loop, where the differential output signal of S2D is used to generate a control signal CTR<4:0> by the DCC.…”

Time‐to‐digital converters—A comprehensive review

“…TDC has been deployed as a key component in some of the applications, namely, ADPLL, 1 ADDLL, 2 clock and data recovery (CDR) circuit, 3 time‐over‐threshold (TOT) positron emission tomography (PET), 4 jitter measurement, 5 time‐of‐flight (TOF) laser radar, 6 TOF PET scanner, 7 silicon photomultiplier SiPM PET, 8 Light Detection And Ranging (LiDAR), 9 digital storage oscilloscope, 10 fluorescence–lifetime imaging microscopy (FLIM), 11 3‐D imaging, 12 Raman spectroscopy, 13 on‐chip temperature sensor 14,15 , time domain ADCs, 16 DC–DC converter, 17 and radio frequency identification (RFID) tag sensor 18 . Earlier, TDC applications limited to high energy physics experiments and later found in ADPLL (all digital phase‐locked loop) as a phase detector.…”

Run‐time calibration scheme for the implementation of a robust field‐programmable gate array–based time‐to‐digital converter

“…Time-to-digital converters (TDCs) measure time intervals for various scientific and engineering applications, such as positron emission tomography (PET) scanners, [1][2][3] time-of-flight PET, 4,5 time-of-flight laser radar, 6 and mass spectrometry. [8][9][10][11][12][13][14][15][16] Although the time resolution achieved using a TDC with an ASIC is superior to that achieved using field-programmable gate array (FPGA) platforms, [8][9][10] TDC circuits have been implemented in FPGA platforms due to their flexible and short establishment time. [8][9][10][11][12][13][14][15][16] Although the time resolution achieved using a TDC with an ASIC is superior to that achieved using field-programmable gate array (FPGA) platforms, [8][9][10] TDC circuits have been implemented in FPGA platforms due to their flexible and short establishment time.…”

“…7 TDCs have been implemented in the analog domain by using application-specific integrated circuits (ASICs) capable of providing high time resolution. [8][9][10][11][12][13][14][15][16] Although the time resolution achieved using a TDC with an ASIC is superior to that achieved using field-programmable gate array (FPGA) platforms, [8][9][10] TDC circuits have been implemented in FPGA platforms due to their flexible and short establishment time. Thus, numerous FPGA-based TDCs have been proposed recently.…”