A 14nm FinFET transistor-level 3D partitioning design to enable high-performance and low-cost monolithic 3D IC

Shi, Jiajun; Nayak, Deepak Kumar; Banna, Srinivasa; Fox, Robert; Samavedam, Srikanth; Samal, Sandeep Kumar; Lim, Sung Kyu

doi:10.1109/iedm.2016.7838032

Cited by 19 publications

(7 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…8b-d). Note that similar V t is predicted for M3D with FinFET [67]. Previous works have highlighted this vertical electrical interference issue between interconnects and devices [9] in different tiers with measured results, and placing conductive thin films between tiers for interference screening (Fig.…”

Section: Electrical Interference and Their Screening By 2d Materialssupporting

confidence: 73%

Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges

Jiang

Parto

Cao

et al. 2019

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

As a possible pathway to continue Moore's law indefinitely into the future as well as unprecedented beyond-Moore heterogeneous integration, we examine the prospects of building monolithic 3D integrated circuits (M3D-IC) with atomically-thin or 2D van der Waals materials in terms of overcoming the major drawbacks of current 3D-ICs, including low process thermal budget, inter-tier signal delay, chip-overheating, and inter-tier electrical interference problems. Our holistic evaluation includes consideration of the electrical performance, thermal issues, and electromagnetic interference as well as attention to the synthesis methods necessary for low-temperature transfer-free 2D materials growth in M3D fabrication. Both in-plane and out-of-plane heat-dissipation in 3D-ICs made with 2D materials are evaluated and compared with those of bulk materials. Electrostatic and high-frequency electric-field simulations are conducted to assess the screening effect by graphene and effect of scaling down the inter-layer dielectric (ILD) thickness. Our analysis reveals for the first time that the 2D-based M3D integration can offer >ten-folds higher integration density compared with through-silicon-via (TSV)-based 3D integration, and >150% integration density improvement with respect to conventional M3D integration. Therefore, 2D materials provide a significantly better platform, with respect to bulk materials (such as Si, Ge, GaN), for realizing ultra-high-density M3D-ICs of ultimate thinness for next-generation electronics. INDEX TERMS 3D integration, 2D layered materials, h-BN, MoS 2 , WSe 2 , beyond-Moore integration, electromagnetic interference, graphene, interconnect, interface thermal conductivity, Moore's law, thermal profile, vertically-stacked devices.

show abstract

Section: Electrical Interference and Their Screening By 2d Materialssupporting

confidence: 73%

Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges

Jiang

Parto

Cao

et al. 2019

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

show abstract

“…There are three types of partitions possible in Mono3D: block-, gate-, and transistor-level. While there are several works in gate-and transistor-level partition [11][12][13], we focus on a two-tier block-level partition in this paper, in which 2D IP blocks can be used in the design process of Mono3D.…”

Section: Related Workmentioning

confidence: 99%

Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators

Shukla

Nemtzow

Pavlidis

et al. 2021

Proceedings of the 26th Asia and South Pacific Design Automation Conference

View full text Add to dashboard Cite

We propose a design automation methodology to help design of energy-efficient Mono3D DNN accelerators with safe on-chip temperatures for mobile systems. We introduce an optimizer capable of investigating the impact of different aspect ratios of the chip and chip footprint specifications, and selecting energy-efficient accelerators under user-specified thermal and performance constraints. We also demonstrate that using our optimizer we can reduce energy consumption by 1.6× and area by 2× with a maximum of 9.5% increase in latency compared to a Mono3D DNN accelerator optimized only for performance.

show abstract

“…Since each layer is sequentially processed with interlayer dielectric (ILD) insulation and interlayer via (ILV) connection, M3D integration enables the alignment accuracy and feature size of both devices and ILVs to be scaled toward the sub‐100 nm level 8 . Such high‐density direct connection vias reduce the wire length and thickness of each layer, and the low‐κ ILD layers lower the coupling parasitic capacitance of the adjacent layers, which contributes to suppressing the heat dissipation and RC delay 9 . In spite of some prototypes with an M3D architecture being demonstrated since 1987, the thermal budget issue hinders the growth of high‐quality semiconductors and then high‐performance transistors at upper layers, attributed to the temperature‐compromised fabrication process 10–13 .…”

Section: Introductionmentioning

confidence: 99%

Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits

Fan

Cheng

et al. 2023

InfoMat

View full text Add to dashboard Cite

Carbon nanotube field‐effect transistors (CNT FETs) have been demonstrated to exhibit high performance only through low‐temperature fabrication process and require a low thermal budget to construct monolithic three‐dimensional (M3D) integrated circuits (ICs), which have been considered a promising technology to meet the demands of high‐bandwidth computing and fully functional integration. However, the lack of high‐quality CNT materials at the upper layer and a low‐parasitic interlayer dielectric (ILD) makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance. In this work, we demonstrate a multilayer stackable process for M3D integration of high‐performance aligned carbon nanotube (A‐CNT) transistors and ICs. A low‐κ (~3) interlayer SiO2 layer is prepared from spin‐on‐glass (SOG) through processes with a highest temperature of 220°C, presenting low parasitic capacitance between two transistor layers and excellent planarization to offer an ideal surface for the A‐CNT and device fabrication process. A high‐quality A‐CNT film with a carrier mobility of 650 cm2 V–1 s–1 is prepared on the ILD layer through a clean transfer process, enabling the upper CNT FETs fabricated with a low‐temperature process to exhibit high on‐state current (1 mA μm–1) and peak transconductance (0.98 mS μm–1). The bottom A‐CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication. As a result, 5‐stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100 μm2, representing the fastest and the most compact M3D ICs to date.

show abstract

A 14nm FinFET transistor-level 3D partitioning design to enable high-performance and low-cost monolithic 3D IC

Cited by 19 publications

References 5 publications

Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges

Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges

Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators

Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits

Contact Info

Product

Resources

About