A 14-GHz 8-bit Direct Digital Synthesizer in InP DHBT Technology

Li, Xiaopeng; Zhang, Yi; Wang, Zhigong; Zhang, Youtao; Zhang, Min; Cheng, Wei; Gao, Hao

doi:10.1109/rfit.2019.8929198

Cited by 3 publications

(8 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…• Frequency points : This DDS has 12-bits phase resolution which is capable of generating F P = 2 12−1 = 2048 frequency points which is largest number (jointly with [4]) in DDS beyond 15 GHz clock [59]. Other reported DDS has the maximum phase resolution of 8-bit (128 frequency points) for such high speed DDS [43].…”

Section: Technology Selection and Goalsmentioning

confidence: 97%

“…It limits the size of the accumulator (9-bits), eventually restricting the frequency points and SFDR quality of the DDS as well. It is the reason behind all the InP DDS so far has less than 256 and SFDR less than 30 dBc for above 10 GHz clock DDS [43]. Comparing SiGe based DDS [5] and InP based DDS [3], the F clk P ratios are 34.56 GHz/W and 3.38 GHz/W respectively.…”

Section: Power Consumption Integration Capability Frequency Resolutionmentioning

confidence: 99%

“…Since DDS uses a large number of digital circuits, the number of an active transistor operating at high speed pose significant challenges not only during circuit design and layout but also during production. The number of transistors used for DDS at high speed is on the edge of the manufacturing capability of the IC foundry [43]. Such a large DDS circuit yield is poor, thus, special design effort in advance should be taken.…”

Section: Dds Challengesmentioning

confidence: 99%

“…• F clk : This DDS aims the highest DDS clock frequency in SiGe and third highest DDS clock frequency in any technology [43], [5], [59].…”

Section: Technology Selection and Goalsmentioning

confidence: 99%

“…However, it doesn't reduce the frequency resolution or FCW input control. In high speed DDS; the DAC appears to be 5-10 bits in practice [59], [39], [43]. Both NL-DAC and TSC based can used for sine mapping in high-speed DDS, however, the power consumption to clock ratios are much higher (see chapter (Table 1.3)).…”

Section: Rom-less Dds Architecturementioning

confidence: 99%

See 4 more Smart Citations

SiGe based ROM-less 18.5 GHz clock direct digital synthesizer design and characterization

Shrestha¹

View full text Add to dashboard Cite

The requirement of the versatile signal generator has always been evident in modern RF and communication systems. The most conventional technique, voltage control oscillator (VCO), has inferior phase noise and narrow bandwidth despite its operating frequency can be up to the sub-THz regime. Its phase noise influenced by a various parameter associated with the oscillator circuit e.g. transistor size \& noise, bias current, noise leaking from the bias supply etc. The bandwidth is limited because the input voltage \& the output frequency of the VCO is not strictly linear over the tuning range. The phase noise and SFDR of the VCO output are enhanced by using the phase-lock technique. The phase-locked loop (PLL) uses the feedback system locking the reference frequency set by the VCO. However, the settling time of the PLL is higher due to a feedback control loop. The higher settling time increases the frequency switching time between PLL outputs. IG-oscillators is suitable for multi-GHz range and wide bandwidth application. Signal generation can alos be achieved by the free-electron radiation, optical lasers, Gunn diodes as well and they can operate even at the THz domain. All these signal generators suffer from slow frequency switching, lack of digital controllability, and advance modulation capability even though their frequency of operation is THz regime. Alternatively, the AWG (arbitrary wave generator) can produce a wide range of frequencies with low phase noise, including digital controllability. One of the vital components of the AWG is the direct digital synthesiser (DDS). Generally, it is composed of a phase accumulator, digital to analogue converter, sine mapping circuits and low pass filter. It needs a reference clock that acts as samples of the DDS outputs. Its output frequency can be varied by applying an appropriate digital input code. But high-speed DDS has several limitations; such as low number of output frequency points, lack of phase control unit, high power consumptions etc. This work addresses such limitations.

show abstract

Section: Technology Selection and Goalsmentioning

confidence: 97%

Section: Power Consumption Integration Capability Frequency Resolutionmentioning

confidence: 99%

Section: Dds Challengesmentioning

confidence: 99%

“…• F clk : This DDS aims the highest DDS clock frequency in SiGe and third highest DDS clock frequency in any technology [43], [5], [59].…”

Section: Technology Selection and Goalsmentioning

confidence: 99%

Section: Rom-less Dds Architecturementioning

confidence: 99%

See 3 more Smart Citations

SiGe based ROM-less 18.5 GHz clock direct digital synthesizer design and characterization

Shrestha¹

View full text Add to dashboard Cite

show abstract

A Nonlinear Transmission Line with Harmonic sub-THz Power Generation in a 40 nm CMOS Technology

Gao

Chen

Wang

2021

2021 46th International Conference on Infrared, Millimeter and Terahertz Waves (IRMMW-THz)

View full text Add to dashboard Cite

Evolution Trends and Paradigms of Low Noise Frequency Synthesis and Signal Conversion Using Silicon Technologies

2022

View full text Add to dashboard Cite

Silicon technologies for HF applications have been proven for more than two decades, and technologies have greatly evolved. Whether CMOS or BiCMOS technologies, the unique combination of radio frequency, baseband, and digital functions allow a very high level of integration. While it is possible to achieve fully integrated transceivers, the major advantages of these silicon technologies lie mainly in their unparalleled performance in the field of frequency synthesis and frequency conversion. We propose in this paper a review of the major results obtained on these RF components since the beginning of the 2000s, also considering the impact of the technology node. The back-end of line (BEOL) process on which depends the quality of microwave monolithic integrated circuits (MMICs) is briefly presented in the introductory part. If circuit performances are tightly bound to the active devices (i.e., the heterojunction bipolar transistor SiGe HBT or CMOS transistor), passive elements (i.e., quality factor of inductors and varactors, losses of transmission, or interconnection lines) as well as the definition of the substrate also play a major role. The core of the article is oriented toward the noise of synthesized signals and frequency conversion. Frequency synthesis is presented through the analog design of a voltage-controlled oscillator (VCO) or through the direct digital frequency synthesis (DDFS), for which respective figures of merit are presented and discussed in a second section. The spectral purity of the oscillators being decisive in the definition of the throughput of a link is approached through the comparison of different figures of merit (FoM) for a set of circuits achievements over the selected period. If the realization of free oscillators is closely bound to the phase-locked loop (PLL)-type control loop for VCOs, the DDFS solution provides more direct and more flexible alternative at first sight. Therefore, these two solutions are analyzed collectively. Finally, the oscillator integrated in the transmitter or receiver supplies the needed LO (local oscillator) power to the frequency mixer in the frequency conversion module: henceforth, the third part of this study focuses on high-frequency mixer realizations. We thus consider this LO power in some advanced figure of merit mentioned in the second section. The design trade-off of the mixer is presented in an approach combining LO (conversion gain, channel isolation, and phase noise) and RF (HF noise figure and channel isolation) constraints. The final section provides a summary of the results and trends mentioned in the paper.

show abstract

A 14-GHz 8-bit Direct Digital Synthesizer in InP DHBT Technology

Cited by 3 publications

References 10 publications

SiGe based ROM-less 18.5 GHz clock direct digital synthesizer design and characterization

SiGe based ROM-less 18.5 GHz clock direct digital synthesizer design and characterization

A Nonlinear Transmission Line with Harmonic sub-THz Power Generation in a 40 nm CMOS Technology

Evolution Trends and Paradigms of Low Noise Frequency Synthesis and Signal Conversion Using Silicon Technologies

Contact Info

Product

Resources

About