The highly parallel artificial neural systems based on transistor-like devices have recently attracted widespread attention due to their high-efficiency computing potential and the ability to mimic biological neurobehavior. For the past decades, plenty of breakthroughs related to synaptic transistors have been investigated and reported. In this work, a kind of photoelectronic transistor that successfully mimics the behaviors of biological synapses has been proposed and systematically analyzed. For the individual device, MXenes and the self-assembled titanium dioxide on the nanosheet surface serve as floating gate and tunneling layers, respectively. As the unit electronics of the neural network, the typical synaptic behaviors and the reliable memory stability of the synaptic transistors have been demonstrated through the voltage test. Furthermore, for the first time, the UV-responsive synaptic properties of the MXenes floating gated transistor and its applications, including conditional reflex and supervised learning, have been measured and realized. These photoelectric synapse characteristics illustrate the great potential of the device in bio-imitation vision applications. Finally, through the simulation based on an artificial neural network algorithm, the device successfully realizes the recognition application of handwritten digital images. Thus, this article provides a highly feasible solution for applying artificial synaptic devices to hardware neuromorphic networks.

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Signal acquisition systems for emerging applications, such as implantable or unobtrusively wearable autonomous sensors, large sensor arrays, or wireless self-powered sensors, require a minuscule form factor and very low power consumption. For example, the power available from a state-of-the-art 1mm 3 solid-state thin-film battery is limited to 4nW for a 10yr lifetime [1], and a 1mm 3 energy harvester attached to a running person delivers only 7.4nW [2]. While several low-power signal acquisition systems have been proposed [3][4][5], their consumption is still in the 20-to-1000nW range. Circuits aiming at low absolute power often result in low power-efficiency (due to overhead), high PVT sensitivity and poor reliability (due to the use of simplistic circuitry). This work presents a fully-integrated signal acquisition IC with six-fold lower power consumption than prior art, which provides state-of-the-art power-efficiency and ensures enough circuit reliability, precision and bandwidth to enable practical applications.Figure 21.2.1 presents the implemented system, which requires only 5 external wires and a single 0.6V supply. It contains a 370Hz BW amplifier, a 10b 1kS/s ADC, a serial data interface, a clock generator and voltage and current biasing. A common-mode reference VCM is created by two diode connected PMOS devices in sub-threshold mode. A standard bootstrapped current reference circuit creates two bias currents: one for the amplifier stages (I amp ), and one for the clock generator (I clk ). To generate the clock, I clk is integrated on a capacitor C clk of 10fF. A feedback loop resets C clk after a threshold voltage is reached, thus creating a saw-tooth wave as illustrated. A chain of 6 inverters is added to generate a sufficiently long on-pulse for the 16kHz output clock CLK16. The first inverter uses long transistors to avoid short-circuit power loss due to the saw-tooth input signal. A 4b counter divides CLK16 by 16 to create a 1kHz ADC clock. The counter also drives a MUX to serialize the 10b from the ADC, preceded by a fixed 6b header. Thus, the output data can be decoded by a receiving chip without requiring additional synchronization signals.The AC-coupled amplifier is shown in Fig. 21.2.2. The capacitor ratio C i /C n = 40pF/1pF sets the differential gain to 32dB. This gain maximizes the overall DR and power-efficiency by equalizing the noise contributions from the amplifier and the ADC when referred to the system's input. Capacitors C p (1pF) create a positive feedback loop to increase the input impedance to >2GΩ up to 200Hz according to simulations. The DC servo loop (DSL) implements 3 functions: first, the feedback reduces the amplifier's offset. Second, the common-mode feedback (CMFB) of the DSL tunes the DSL's output common-mode and hence the input biasing of A1 to the VCM reference. Third, the DSL sets the high-pass corner of the amplifier. Amplifiers A1, A2, and DSL are all implemented with inverter-based sub-threshold amplifiers for best power-efficiency ( Fig. 21.2.2). Bias V B is derived...

DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal.If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the "Taverne" license above, please follow below link for the End User Agreement:

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