A 14-b 20-MS/s 78.8 dB-SNDR Energy-Efficient SAR ADC With Background Mismatch Calibration and Noise-Reduction Techniques for Portable Medical Ultrasound Systems

Liang, Yuhua; Li, Changying; Liu, Shubin; Zhu, Zm

doi:10.1109/tbcas.2022.3147954

Cited by 56 publications

(7 citation statements)

References 22 publications

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“…The proposed design is superior in terms of resolution and power consumption when compared with other design at 45nm technology node. Li et al (2022) [4] depicted less power consumption than the proposed design but at the cost low value of resolution bits. Comparing to 90nm, proposed design work at lower voltage level, high resolution and consumes approximately 10 times less power.…”

Section: Performance Specifications Of Presented Design Of Sar Adcmentioning

confidence: 82%

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High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

Singh,

Tripathi,

Kumar

2024

JICS

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In this study, a high-performance 16-bit, 500 MS/s successive approximation register analog-to-digital con-verter (SAR-ADC) with variable body biasing (VBB) for re-ducing sub-threshold leakage is designed and optimized. The suggested ADC architecture makes use of a voltage threshold complementary metal-oxide-semiconductor (VTCMOS) cir-cuit with Widlar current mirror technology to efficiently con-sume 39.2 μW at an operating voltage of 1.0 V. Notably, the optimized ADC achieves outstanding performance measures, such as a signal-to-noise and distortion ratio (SNDR) of 97 dB and a total harmonic distortion (THD) of -97.97 dB, which are crucial markers of the ADC's accuracy and fidelity. An over-view of the growing need for high-resolution ADCs in contem-porary high-speed data conversion systems opens the study. The main goal of this effort is to improve overall ADC per-formance and tackle the problem of sub-threshold leakage. The Widlar current mirror technology and the VTCMOS cir-cuit are integrated for enhanced linearity, decreased current mismatch errors, and minimized leakage current. This inte-gration is highlighted in the full explanation of the ADC de-sign. The advent of the VBB approach as a successful method of leakage reduction is a significant contribution to this re-search. The theoretical foundations and workings of the VBB technique are discussed, and thorough simulations and tests are used to assess how the VBB technique affects leakage cur-rent and circuit performance. The SAR-ADC design and simulations were carried out using Cadence Virtuoso soft-ware.

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Section: Performance Specifications Of Presented Design Of Sar Adcmentioning

confidence: 82%

“…Since it can greatly affect power consumption and overall circuit performance, leakage current is a serious issue in low-power systems. The suggested design successfully minimizes power consumption by utilizing the VTCMOS circuit [9].…”

Section: Introductionmentioning

confidence: 99%

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

Singh,

Tripathi,

Kumar

2024

JICS

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“…As shown, the achieved Schreier figure of merit (FoM S ) is better than all the ADC except for that in Ref. [36]. From the aspect of the effective noise under a given reference voltage, the specification of effective total noise is defined and compared in Table 1.…”

Section: Measurement Resultsmentioning

confidence: 98%

“…The delay unit (delay by N/2) is included to match the phase shift between the input digital code and the filtered expected signal. The presented calibration scheme differs from the classical four-parameter curve-fitting based LMS calibration [35] only in the way of generating the expected reference sinusoid signal. Thus, under the condition an ideal input sinusoid signal for calibration, both approaches would exhibit similar convergence speed and accuracy.…”

Section: Cdac Mismatch Calibration With Fir-based Signal Extractionmentioning

confidence: 99%

A 16-bit 18-MSPS flash-assisted SAR ADC with hybrid synchronous and asynchronous control logic

Ji,

Zhou

et al. 2024

J. Semicond.

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This paper presents a 16-bit, 18-MSPS (million samples per second) flash-assisted successive-approximation-register (SAR) analog-to-digital converter (ADC) utilizing hybrid synchronous and asynchronous (HYSAS) timing control logic based on an on-chip delay-locked loop (DLL). The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter (CDAC) than the synchronous and asynchronous SAR ADC. Therefore, the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent. In addition, the foreground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter (FIR-BPF) based least-mean-square (LMS) algorithm in an off-chip FPGA (field programmable gate array). Fabricated in 40-nm CMOS process, the prototype ADC achieves 94.02-dB spurious-free dynamic range (SFDR), and 75.98-dB signal-to-noise-and-distortion ratio (SNDR) for a 2.88-MHz input under 18-MSPS sampling rate.

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“…The most significant bit (MSB) is compared first, then the least significant bit (LSB), progressively improving the digital output with each comparison. By successively approximating the input voltage with a binary search until the requisite precision is obtained, the SAR ADC delivers great resolution [11]. The 16-bit SAR ADC may offer a fine-grained representation of the analog input signal thanks to its resolution of 216 or 65,536 discrete levels as shown in figure 1.…”

Section: Design Of Sar Adcmentioning

confidence: 99%

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Singh,

Tripathi,

Mahmud

2024

Eng. Res. Express

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This study gives a thorough analysis of the performance of a 45 nm CMOS process-designed 16-bit 500 MS/s successive approximation register analog-to-digital converter (SAR-ADC). 16-bit R-2R DAC double-tail dynamic latch, Widlar current method, variable body-biasing technique, sample and hold block, 16-bit SAR, and 16-bit latch are used to design proposed SAR-ADC block. The SAR-ADC design and simulations were carried out using Cadence Virtuoso software. This powerful electronic design automation (EDA) tool facilitated the design, layout, and simulation of the ADC, ensuring a comprehensive analysis of its performance characteristics. MATLAB was used for post-simulation data analysis, processing, and visualization. The proposed SAR-ADC is compared with few existing examples listed as ADS8881, LTC2380-16, ADS8344, LTC2368, and MAX11156 on the performance metrics including signal-to-noise ratio (SNR), figure of merit (FOM), total harmonic distortion (THD), resolution, delay, power consumption and Figure of Merit (FOM). This work is highlighting different aspects of the suggested architecture and demonstrates how it outperforms benchmark of ADCs in terms of power usage, SNR, THD, and FOM. A SAR-ADC attains a power consumption of 39.2 µW while operating at sampling frequency of 500 MS/s at supply voltage of 1V. The results provide fresh perspectives for potential improvements in existing work in terms of reduction in power consumption and high-speed ADC at 16-bit resolution and also Jitter is scrutinized across various stages of the SAR-ADC. The proposed low power, high speed and high-resolution SAR ADC is targeted for high-quality analog-to-digital signal conversion useful in industrial automation systems, medical devices, IoT and audio processing modules.

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A 14-b 20-MS/s 78.8 dB-SNDR Energy-Efficient SAR ADC With Background Mismatch Calibration and Noise-Reduction Techniques for Portable Medical Ultrasound Systems

Cited by 56 publications

References 22 publications

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

A 16-bit 18-MSPS flash-assisted SAR ADC with hybrid synchronous and asynchronous control logic

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

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A 14-b 20-MS/s 78.8 dB-SNDR Energy-Efficient SAR ADC With Background Mismatch Calibration and Noise-Reduction Techniques for Portable Medical Ultrasound Systems

Cited by 56 publications

References 22 publications

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

A 16-bit 18-MSPS flash-assisted SAR ADC with hybrid synchronous and asynchronous control logic

Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications

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Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications