A 14∼23 GHz CMOS MMIC distributed doubler with a 22-dB fundamental rejection

Abstract

A broadband MMIC frequency distributed doubler fabricated by 0.18-μm CMOS technology has been designed to operate from 14 to 23 GHz. In order to reject the fundamental signals, the traditional low-pass drain line was replaced by a high-pass structure. The topology can improve the fundamental rejection without additional balanced structure, thus the chip size can be minimized. This measured conversion loss is less than 14 dB and the fundamental rejection is better than 22 dB for the output frequency between 14 and 23 GHz. The chip size is only 0.54 x 0.38 mm 2 .

Recent development of millimeter-wave CMOS monolithic integrated circuits

“…We have also developed a frequency doubler in 0.13-m CMOS [41]. The doubler is a distributed doubler using a high-pass drain line topology.…”

A novel complementary push-push frequency doubler with negative resistor conversion gain enhancement

“…Single-transistor FD is composed of a single transistor with matching network [1,2], but the conversion gain (CG) is low. Distributed FD [3] and Distributed FD with current-reuse technical [4] have been demonstrated, which provides higher CG. Both single-transistor and distributed FD provide low fundamental rejection (FR) and require extra filters for FR improvement.…”