A 12b 50MSPS 34mW pipelined ADC

Yu, Hui; Chin, S.W.; Wong, B.C.

doi:10.1109/cicc.2008.4672080

Cited by 10 publications

(11 citation statements)

References 5 publications

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“…the proposed structure in [11] may not be suitable for the ADCs that are expected to run at the maximum achievable sampling rate for a given resolution and technology, Because the opamp used in the proposed first stage needs to be faster, simultaneously meaning more power consumption, than the one in the traditional first stage. The proposed structures in [12,13], taking use of some techniques proposed in [14], need additional clocks of different duty cycle. This paper combines SHA-less, opamp-sharing, multibit-per-stage techniques together into the whole ADC, including the first stage.…”

Section: Introductionmentioning

confidence: 99%

“…Complex calibration schemes and/or circuit techniques [4][5][6][7][8], which are usually needed to enhance the linearity and/or correct the mismatches such as compensating low gain, low bandwidth and incomplete settling of opamps, need complicated algorithm, additional digital circuitry and extra calibration cycles. SHA-less and opamp-sharing are two important ways for low-power pipelined ADC design [9][10][11][12][13]. However, they also bring some drawbacks affecting the ADC performance, such as nonlinearity and distortion.…”

Section: Introductionmentioning

confidence: 99%

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A 1.8-V 11-bit 40-MS/s 21-mW pipelined ADC

Fan

Ren

et al. 2010

Analog Integr Circ Sig Process

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A set of low-power techniques is proposed to realize low power design in pipeline analog-to-digital converter (ADC). These techniques include removing the active S/H (i.e., SHA-less), sharing the opamp between the adjacent multi-bit-per-stages, low-power high-efficiency high-swing amplifier technique. Also, a new sampling topology is proposed to minimize aperture error by matching the time constant between the two input signal paths. All these skills are verified by simulation in the design of the 1.8-V 11-bit 40-MHz ADC in a 0.18-lm CMOS process with power dissipation 21-mW, signal-tonoise-and-distortion ratio (SNDR) 65-dB, effective number of bit (ENOB) 10.5-bit, spurious free dynamic range (SFDR) 78-dB, total harmonic distortion (THD) -75.4-dB, signal-to-noise ratio (SNR) 65.4-dB and figure-of-merit (FOM) 0.18 pJ/step.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 1.8-V 11-bit 40-MS/s 21-mW pipelined ADC

Fan

Ren

et al. 2010

Analog Integr Circ Sig Process

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“…(V ref p − V ref n ) can be guaranteed. Techniques such as forward body biasing [79] or level shifting with boosted supply voltages and additional SF stages [80] will need to be employed in the RVBuffer which will increase design complexity. With a lower input range for the ADC and assuming that the total DAC capacitance remains unchanged, a pre-amplifier for the dynamic comparator will become inevitable to reduce the noise at the cost of increased power consumption [81].…”

Section: Circuit Details Of the Reference Voltage Buffermentioning

confidence: 99%

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Harikumar¹

2016

Linköping Studies in Science and Technology. Dissertations

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Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these distributed WSNs are often low, ultra-low-power ADCs with low sampling rates are required. The advent of new wireless standards with ever-increasing data rates and bandwidth necessitates ADCs capable of meeting the demands. Wireless standards such as GSM, GPRS, LTE and WLAN require ADCs with several tens of MS/s speed and moderate resolution (8-10 bits). Since these ADCs are incorporated into battery-powered portable devices such as cellphones and tablets, low power consumption for the ADCs is essential.The first contribution is an ultra-low-power 8-bit, 1 kS/s successive approximation register (SAR) ADC that has been designed and fabricated in a 65-nm CMOS process. The target application for the ADC is an autonomously-powered soil-moisture sensor node. At V DD = 0.4 V, the ADC consumes 717 pW and achieves an FoM = 3.19 fJ/conv-step while meeting the targeted dynamic and static performance. The 8-bit ADC features a leakage-suppressed S/H circuit with boosted control voltage which achieves > 9-bit linearity. A binary-weighted capacitive array digital-to-analog converter (DAC) is employed with a very low, custom-designed unit capacitor of 1.9 fF. Consequently the area of the ADC and power consumption are reduced. The ADC achieves an ENOB of 7.81 bits at near-Nyquist input frequency. The core area occupied by the ADC is only 0.0126 mm 2 .The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and implemented in 65 nm CMOS aimed at communication applications. For medium-tohigh sampling rates, the DAC reference settling poses a speed bottleneck in chargeredistribution SAR ADCs due to the ringing associated with the parasitic inductances. Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip reference voltage buffers. The estimation of important design parameters of the buffer as well iv critical specifications such as power-supply sensitivity, output noise, offset, settling time and stability have been elaborated upon in this dissertation. The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages. The 10-bit SAR ADC utilizes split-array capacitive DACs to reduce area and power consumption. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the ...

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“…In pipelined ADCs or SAR ADCs, which utilize only a fraction of supply voltage as full scale range, a reference buffer with sufficient driving capability is required to provide accurate voltage references [1]. Furthermore, on-chip supply or substrate noise must be sufficiently attenuated with high PSRR, which is often achieved by using a large bandwidth error correcting amplifier in a negative feedback loop [1].…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, on-chip supply or substrate noise must be sufficiently attenuated with high PSRR, which is often achieved by using a large bandwidth error correcting amplifier in a negative feedback loop [1]. Low power and low driving impedance is usually achieved by using source follower driving stage and its relative accuracy is corrected by error amplifiers.…”

Section: Introductionmentioning

confidence: 99%

A low-power reference buffer with high PSRR and low crosstalk for time-interleaved ADCs

Song

Kim

Lee

2013

IEICE Electron. Express

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A low power reference buffer is proposed to achieve high PSRR and less crosstalk between channels for time-interleaved analog-to-digital converters (ADCs). A conventional approach requires enough bandwidth in feedback amplifiers to suppress high frequency supply noise, which tends to increase power consumption. Furthermore the number of output drivers that share error amplifier output is unavoidably limited due to the coupling across ADC channels. We propose design techniques to improve the corner frequency of power supply rejection ratio (PSRR) by a factor of 100 and the cross-channel isolation by 20 dB without drawing more current.

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A 12b 50MSPS 34mW pipelined ADC

Cited by 10 publications

References 5 publications

A 1.8-V 11-bit 40-MS/s 21-mW pipelined ADC

A 1.8-V 11-bit 40-MS/s 21-mW pipelined ADC

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

A low-power reference buffer with high PSRR and low crosstalk for time-interleaved ADCs

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