A 125MHz burst mode 0.18μm 128Mbit 2 bits per cell flash memory

Castro, H.A.; Augustine, K.; Balasubrahmanyam, S.; Bressie, T.; Chandramouli, S.; Christensen, G.; Dayley, M.; Elmhurst, D.; Fan, Kui; Goldman, M.; Haid, C.; Haque, Rezaul; Ishac, M.; Khandaker, Murshed; Kreifels, J.A.; Li, B.; Loe, K.; Ly, T.; Marvin, F.; Melcher, R. L.; Monasa, S.; Nambiar, Rohitkrishna Rajendran; Ngo, Q.H.; Padilla, Ricardo Edgardo Quintanilla; Pathak, B.; Rahman, Anisur; Rajagopal, Ramkumar; Ramamurthi, K.; Saini, Suman; Sayed, AH; Sharif, I.; Srinivasan, Balaji; Szwarc, M.; Vadlamudi, G.; Viajedor, V.; Zeng, R.W.

doi:10.1109/vlsic.2002.1015111

Cited by 5 publications

(3 citation statements)

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“…(5) C tot represents the total capacitance estimated from the total number of transistors in the circuit. Total capacitance of the binary circuits is estimated by multiplying the number of equivalent twoinput NAND gates with their input capacitance as shown in Equation (6). Correspondingly, Equation (6) is also used for the quaternary circuits using two-input MIN gate equivalents.…”

Section: B Multiplier Circuit Dynamic Power Dissipationmentioning

confidence: 99%

“…The increased data density due to the higher informational content per conductor is one of the main benefits of MVL circuit implementations [1][2][3]. Several transistor-based implementation technologies have been proposed to realize MVL circuits [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. Conventional electronic MVL circuits can be categorized as currentmode, voltage-mode, or mixed-mode circuits.…”

Section: Introductionmentioning

confidence: 99%

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Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits

Datla

Thornton

2010

2010 40th IEEE International Symposium on Multiple-Valued Logic

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Section: B Multiplier Circuit Dynamic Power Dissipationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits

Datla

Thornton

2010

2010 40th IEEE International Symposium on Multiple-Valued Logic

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“…The reading concept generally utilized in previously reported multilevel NOR products [4,5] applies a fixed (5 to 6V) gate voltage to the matrix cell and to a set of reference cells whose threshold represents the boundary between the different levels. The sense amplifier(s) compare (in parallel or sequentially) the currents of the array cell with the reference and produces the two bits.…”

mentioning

confidence: 99%

A 125MHz burst-mode flexible readwhile-write 256Mbit 2b/c 1.8V NOR flash memory

Villa¹,

Vimercati²,

Schippers³

et al.

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.

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Multilevel technology flash memory devices have been introduced [1] to obtain the low silicon cost and the high density required by a wide range of applications. Read access time and burst frequency have been improved and dual functionality has been obtained [2,3], in line with the requests of the most demanding wireless applications. The 2b/cell 256Mb memory in this paper features a 125MHz read burst speed and flexible read-whilewrite through the introduction of an voltage-ramp reading concept.The reading concept generally utilized in previously reported multilevel NOR products [4, 5] applies a fixed (5 to 6V) gate voltage to the matrix cell and to a set of reference cells whose threshold represents the boundary between the different levels. The sense amplifier(s) compare (in parallel or sequentially) the currents of the array cell with the reference and produces the two bits. The main challenge and drawback of this concept is tied to the wide current range in which the cell is required to operate (from few uA to several tens of uA). Large currents cause parasitic drops in the array and selector, cell gain variations have a major impact making difficult to narrow the levels to improve reliability and facilitate scaling. The proposed approach operates all cells in a low, fixed current range which minimizes the impact of parasitic resistances and of gain variations.A conventional NOR flash memory architecture is used. Reading and verify operations are performed applying a fast, linear voltage ramp to the reference and matrix cell's gate ( Fig. 2.5.1). The comparison of a local current reference against the cell's current produces a trigger. A time slot exists between two reference triggers. The matrix cell's level is determined by comparing the time difference between matrix and reference cells trigger points. The reference trigger information is driven to the matrix sense amplifiers as a digital bus. The trigger generated by the matrix sense amplifier latches the reference bus whose content digitally determines the cell level (11, 10, 01, 00).A double differential-stage sense amplifier (Fig. 2.5.2) is used. The first stage works as a pre-charger and current to voltage converter. The second stage is a differential comparator with a digital output. The sense amplifier pre-charges the bitline and as the pre-charging is completed, I ref will flow through the resistor R0. When the cell's V th is reached, the current through the bitline increases and when I bl is equal to I ref the sense amplifier produces the trigger; the cell is then cut off by lowering the drain voltage. Figure 2.5.3 further illustrates the operation: after bitline precharge, the voltage ramp turns on in sequence the three reference cells (R1,R2,R3) that cause the change of status of the digital bus. The digital bus is latched by the matrix sense amplifier trigger which is caused by I bl exceeding Iref ; the figure shows, as an example, the trigger point of few cells for each level. The dynamic nature of the voltage ramp (tunable in the range of 30n...

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