A 12-bit medium-time analog storage device in a CMOS standard process

Ehlert, M.; Klär, H.

doi:10.1109/4.701284

Cited by 8 publications

(1 citation statement)

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“…6 shows the drop of voltage across the capacitor with time. This is due to the current leakage through the parasitics [7]. It is almost impossible to eliminate the leakage current, which is very much related to the device physics.…”

Section: Digital-to-analog Convertermentioning

confidence: 99%

Ultralow-power high-resolution ADC for biomedical applications

Hiremath

Mallapur

Stojcevski

et al. 2005

Smart Structures, Devices, and Systems II

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This paper presents a fully differential ultra low power successive approximation (SA) Analog-to-digital converter (ADC) for biomedical application. In order to reduce the system power consumption, the building block components of the SA ADC architecture has been opsimised. In addition, the ADC the input voltage swing is scaled down to in order to reduce the slope gain error and the nonlinearity errors. The SA ADC has been implemented in Cadence Analog Design Environment using 0.18-micron CMOS technology. The designed SA ADC operates at a sampling rate of 200S/s at 3V power supply and consumes only 12µW of power at this frequency. The ADC standby power consumption is less than 1µW. The designed 16-bit ADC occupies an area of 0.1 mm 2 and is the smallest in size among its 16-bit counter parts reported in the literature. The proposed 16-bit ADC achieves the differential-non-linearity (DNL) and integral-non-linearity errors (INL) of ± 0.5 LSB and ± 0.3 LSB respectively.

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Section: Digital-to-analog Convertermentioning

confidence: 99%