A 12-bit digitally controlled oscillator with low power consumption

Zhao, Jun; Kim, Yong-bin

doi:10.1109/mwscas.2008.4616813

Cited by 20 publications

(14 citation statements)

References 7 publications

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“…The used inverter circuit is described in Zhao and Kim (2008) and shown in Figure 8(b), which can reach very fine tuning resolutions (< 1 ps). This current steering inverter has devices (P 0 -P 5 ) and (N 0 -N 5 ), which are binary weighted in size and controlled by the control signal CntN.…”

Section: Digitally Controlled Oscillatormentioning

confidence: 99%

A programmable multi-step cyclic Vernier time-to-digital converter

Raymond¹,

Ghoneima²,

Ismail³

2013

IJCAD

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Abstract:A new architecture for a time-to-digital converter (TDC) is presented in this paper. The programmability feature of the new proposed architecture allows for the reusability of the design for various applications requiring different resolution, throughput, area and power constraints. One of the main motives behind this work (besides the programmability feature) is trying to resolve the inherent TDC design tradeoffs between resolution, throughput and complexity. The new TDC was implemented using the TSMC 65 nm technology. A detailed transistor level design along with the system level analysis is presented. For a reliable operation, a new auto calibration scheme is proposed that guarantees the successful operation of the system. Simulation results show the successful operation of the proposed TDC and its ability to auto calibrate itself for any process corner. As an example, for a resolution of 4 ps with an input range of 1 ns, the proposed TDC had a throughput of 45 MS/s while maintaining a DNL of 0.85 LSB and INL of 0.93 LSB.Keywords: time measurement; time-to-digital converters; TDC; data conversion; calibration systems.Reference to this paper should be made as follows: Raymond, M., Ghoneima, M. and Ismail, Y. (2013) 'A programmable multi-step cyclic Vernier time-to-digital converter', Int.

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Section: Digitally Controlled Oscillatormentioning

confidence: 99%

A programmable multi-step cyclic Vernier time-to-digital converter

Raymond¹,

Ghoneima²,

Ismail³

2013

IJCAD

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“…The proposed DCO employs a new approach to increase the delay tuning range using digitally controlled pass transistor arrays and Schmitt triggerbased inverters [15]. The Schmitt trigger-based inverter has a higher VM+ (low-to-high switching threshold) and lower VM− (high-to-low switching threshold) compared to the conventional inverters as shown in Figure 3.…”

Section: Proposed Dco Designmentioning

confidence: 99%

A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

Zhao

Kim

2010

VLSI Design

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A low-power and low-jitter 12-bit CMOS digitally controlled oscillator (DCO) design is presented. The Low-Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters. Performance of the DCO is verified through a novel All Digital Phase-Locked Loop (ADPLL) designed with a unique lock-in process by employing a time-to-digital converter, where both the frequency of the reference clock and the delay between DCO output and DCO clock is measured. A carefully designed reset process reduces the phase acquisition process to two cycles. The ADPLL was implemented using the 32 nm Predictive Technology Model (PTM) at 0.9 V supply voltage, and the simulation results show that the proposed ADPLL achieves 10 and 2 reference cycles of frequency and phase acquisitions, respectively, at 700 MHz with less than 67 ps peak-to-peak jitter. The DCO consumes 2.2 mW at 650 MHz with 0.9 V power supply.

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“…The designs in [28,29] have good resolution, but the inter-stage delay utilizes more short circuit power by stepper slopes in the input stages of CMOS. The nonlinearity in higher code words is still a problem.…”

mentioning

confidence: 99%

“…The nonlinearity in higher code words is still a problem. However, a good idea was used in [28,29] to preserve the linearity in higher code words. They used a chain of tristate buffers in front of a multiplexor to select different delay paths to overcome the nonlinearity.…”

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Two Efficient Dual-Band and Wide-Band Low-Power DCO Designs Using Current Starving Gates, DCV and Reconfigurable Schmitt Triggers in 180 nm

Souri

Ghaznavi‐Ghoushchi

2015

Circuits Syst Signal Process

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Digitally controlled oscillators are the main cores in all-digital phase-locked loops (ADPLL), which are important for determining the range of frequency and power consumption in ADPLLs. In the conventional digitally controlled oscillator (DCO) designs, one single band of operation is assigned to the DCO. The following paper presents a new approach in the design of DCOs, which works in dual-band and wide-band modes with a control unit. In dual-band mode, the DCO works in two different ranges of frequencies simultaneously via digital control bits. The wide-band DCO (WBDCO) works in one wider range of frequencies consecutively. It seems that in the wide-band DCO, the gap width for the dual-band DCO (DBDCO) is zero. The previously mentioned designs allow the designer to have standard frequencies with the help of direct or multiplied frequencies. So, we can have a trade-off between power and performance. This means that we can have low power consumption in low-frequency applications and vice versa. The proposed designs are based on using digitally controlled capacitors, current starving gates and Schmitt triggers in critical points of the DCO loop, while preserving coarse and fine tunings. The non-delay linearity factors are clearly investigated and resolved with the use of a new combined control unit. The simulations of the proposed designs are performed in Hspice with a voltage of VDD = 1.8 v in 180 nm CMOS technology for 64-and 128-bit input coarse codes. Our simulation and evaluation results showed that in the dual-band DCO, a 14.8 ps jitter was calculated at 134 MHz with 1.2131 mW power consumption, while in the wide band with overlap mode, a 68.7 ps jitter was measured at 184.61 MHz

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A 12-bit digitally controlled oscillator with low power consumption

Cited by 20 publications

References 7 publications

A programmable multi-step cyclic Vernier time-to-digital converter

A programmable multi-step cyclic Vernier time-to-digital converter

A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

Two Efficient Dual-Band and Wide-Band Low-Power DCO Designs Using Current Starving Gates, DCV and Reconfigurable Schmitt Triggers in 180 nm

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