A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS

Wu, Meng-Hsuan; Li, Hung-Sung

doi:10.1109/tcsi.2014.2340583

Cited by 41 publications

(8 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The BW DAC switching scheme avoids unnecessary DAC switching, thus reducing the occurrence of DAC switching errors caused by capacitor mismatch. In contrast with the swapping SAR, 6 the proposed switching technique improves both SNDR and SFDR. In this paper, tiny unit capacitors are not used to construct the capacitor array, but high production yield is maintained by using the proposed dual-reference C-DAC architecture.…”

Section: Introductionmentioning

confidence: 97%

“…Capacitor calibration techniques compensate for capacitor mismatch in the foreground 9 or background. A capacitor-swapping SAR ADC 6 improves ADC linearity by interchanging one half of the total capacitance (C 1 ) with the other half of the total capacitance (C 1X = C 2 + C 3 + ... + C 12 ). A capacitor-swapping SAR ADC 6 improves ADC linearity by interchanging one half of the total capacitance (C 1 ) with the other half of the total capacitance (C 1X = C 2 + C 3 + ... + C 12 ).…”

Section: Introductionmentioning

confidence: 99%

“…In general, most SAR ADCs use capacitor-DACs (C-DACs) to maintain high accuracy. [1][2][3][4][5][6] According to Pelgrom's model, 7 a fourfold increase in the dimensions of 2 capacitors yields a twofold decrease in capacitor mismatch. Figure 1 shows an example 12-bit SAR ADC with a binary C-DAC.…”

Section: Introductionmentioning

confidence: 99%

“…10 These calibration techniques correct errors by using digital postprocessing at the cost of additional power consumption. A capacitor-swapping SAR ADC 6 improves ADC linearity by interchanging one half of the total capacitance (C 1 ) with the other half of the total capacitance (C 1X = C 2 + C 3 + ... + C 12 ). The complementary errors caused by most significant bit (MSB) capacitor switching are randomly swapped to reduce third-order harmonic distortion.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

Yen

Tsai

2017

Circuit Theory & Apps

Self Cite

View full text Add to dashboard Cite

This paper presents an energy-efficient 12-bit successive approximation-register A/D converter (ADC). The D/A converter (DAC) plays a crucial role in ADC linearity, which can be enhanced by using larger capacitor arrays. The binary-window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the spuriousfree dynamic range and signal-to-noise-and-distortion ratio. The ADC prototype occupies an active area of 0.12 mm 2 in the 0.18-μm CMOS process and consumes a total power of 0.6 mW from a 1.5-V supply. The measured peak differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The ADC achieves a 64.7-dB signal-tonoise-and-distortion ratio and 83-dB spurious-free dynamic range at a sampling rate of 10 MS/s, corresponding to a peak figure-of-merit of 43 fJ/conversion-step. KEYWORDSA/D converter (ADC), binary window, D/A converter (DAC), successive approximation register (SAR)

show abstract

Section: Introductionmentioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

Yen

Tsai

2017

Circuit Theory & Apps

Self Cite

View full text Add to dashboard Cite

show abstract

“…Researchers have developed various techniques to address this issue. The most common methods are calibration [4][5][6][7] and correction [8][9][10][11]. For calibration, it adjusts the size of the actual capacitors to match the digital weight of each bit.…”

Section: Introductionmentioning

confidence: 99%

Theoretical total harmonic distortion evaluation based on digital to analogue converter mismatch to improve the linearity of successive approximation register analogue to digital converter

Song

Zhang

et al. 2021

IET Circuits, Devices & Syst

View full text Add to dashboard Cite

Mismatch in the binary-weighted capacitive digital-to-analog converter (DAC) greatly affects the linearity of the successive-approximation-register (SAR) ADC by deteriorating the total harmonic distortion (THD). In this study, a theoretical relationship between the THD and the mismatch error of DAC array in SAR ADC is derived through discrete Fourier transform (DFT) analysis of the time-based integral error (TIE) of the ADC's output codes, which has no specific requirement on the type of the input signals. Guided by the theoretical THD expression, the trade-off among the linearity, design complexity, power consumption and chip area can be balanced easily. The presented formula is verified by a design example of 12-bit SAR ADC with dynamic-element-matching (DEM) technique, where the 3-bit LSBs from the SAR ADC are used to generate the randomised DEM state according to the previous THD evaluation. The linearity is enhanced by 9 dB approximately with very low hardware complexity and extremely small extra power consumption of 2 μW. K E Y W O R D Sanalog-to-digital converter, dynamic element matching, successive approximation register, time-based integral error, total harmonic distribution This is an open access article under the terms of the Creative Commons Attribution-NonCommercial-NoDerivs License, which permits use and distribution in any medium, provided the original work is properly cited, the use is non-commercial and no modifications or adaptations are made.

show abstract

A New 1 GS/s Sampling Rate and 400 μV Resolution with Reliable Power Consumption Dynamic Latched Type Comparator

Mahdavi

Poreh

Ataei

et al. 2018

Lecture Notes in Electrical Engineering

View full text Add to dashboard Cite

A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS

Cited by 41 publications

References 14 publications

A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

Theoretical total harmonic distortion evaluation based on digital to analogue converter mismatch to improve the linearity of successive approximation register analogue to digital converter

A New 1 GS/s Sampling Rate and 400 μV Resolution with Reliable Power Consumption Dynamic Latched Type Comparator

Contact Info

Product

Resources

About