A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification

Murmann, Boris; Boser, Bernhard E.

doi:10.1109/jssc.2003.819167

Cited by 418 publications

(187 citation statements)

References 21 publications

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“…The benefit of this scheme is relaxing from the requirement of precision of analog components and is able to continue CMOS device scaling approach [8]. Component errors from all stages are removed by Finite impulse response (FIR) digital filter.…”

Section: Comparison Of Calibration Techniques 1) Nested Backgroumentioning

confidence: 99%

“…This technique for Pipelined ADCs, does not require any accurate calibration signal. The adaptive LMS algorithm [8] has been used to approximate the errors.…”

Section: ) Equalization Based Digital Calibrationmentioning

confidence: 99%

“…ant for decidin nge the residu [8][9][10][11][12][13][14][15][16][17][18][19][20]. Because match.The effe Figure 3 of an ideal tr Since an op-a on-idealities o …”

mentioning

confidence: 99%

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On Calibration Techniques for Pipelined ADCs

Narula¹,

Pandey²

2017

IJET

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The development and designing of advanced pipelined analog to digital converter (ADC) is becoming sophisticated day by day as dimensions and supply voltages used for devices are reducing. As the nanometer technology aids fabricating circuits with small footprints, we require high-performance Pipelined ADCs, which are able to rectify analog circuit non-idealities with digital calibration circuits. Digital background calibration is the most favorable solution instead of making changes in analog components in the deep submicron processes. This paper discusses some of the techniques for digital calibration that have been accepted to realize advanced pipelined ADCs. It was observed that on an average, for every two years, the efficiency of ADCs is enhanced by a factor of two. With constant technology scaling supply voltages have reduced and the devices operate at high speed. A closer inspection on SNDR, SFDR, INL and DNL of pipelined ADCs with different calibration techniques is presented here. Finally, a comparison on various design approaches is made to make a view towards additional enhancement in speed, power efficiency and functioning of ADCs.

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Section: Comparison Of Calibration Techniques 1) Nested Backgroumentioning

confidence: 99%

“…This technique for Pipelined ADCs, does not require any accurate calibration signal. The adaptive LMS algorithm [8] has been used to approximate the errors.…”

Section: ) Equalization Based Digital Calibrationmentioning

confidence: 99%

See 1 more Smart Citation

On Calibration Techniques for Pipelined ADCs

Narula¹,

Pandey²

2017

IJET

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“…To save power, reduce noise and distortion, the ADC adopts the analog front-end with no pre sample and hold. The structure of ADC is shown as Fig.3, which contains 9-stage pipeline body, internal reference generator, clock circuits, control logic, digital calibration and output driver [3] [4] . The 9-stage pipeline who includes a number of multi-stage and each level has multi-bit, disassociates 4 +3 +1.5 x6 +3 respectively, wherein the first stage is the analog front-end protection without sample and hold.…”

Section: System Schemementioning

confidence: 99%

Design of a SoC for Intermediate Frequency Digital Receiver

Liu¹,

Jun²

2016

Proceedings of the 2016 3rd International Conference on Mechatronics and Information Technology

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Abstract. With the development of CMOS technology, the integration and miniaturization have become the trend of electronic devices. This paper proposes a scheme of system on chip (SoC) that realizes the monolithic integration of the intermediate frequency digital receiver based on CMOS technology, which integrates RF receiver front-end, A/D conversion, digital down conversion and baseband processing together. The chip is manufactured by 0.18um CMOS technology, and the area is 7x8mm2 . The test of chip has completed within the RF reception signal range of 0.5~4GHz, The system noise of RF receiving module is below 10dB, the image rejection is greater than 40dB, the SFDR of ADC can reach to 80.22 dB, and the maximum operating frequency of DDC and CPU can arrive up to 100MHz. the test results can meet the requirements of the project evaluation index. The chip has great potential applications in the miniaturization, integration and high reliability of the electronic systems.

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“…Using an open-loop residue amplification technique [9] instead of capacitive feedback opamp-based circuits enable the designer to achieve a low power ADC because openloop gain stages do not require a large DC-gain, thereby simplifying the MDAC circuit. Employing comparators and integrators instead of opamp is another recently introduced innovation [10] that can perform the same response of the opamp but with far less power dissipation.…”

Section: Introductionmentioning

confidence: 99%

A Low-Voltage Low-Power Opamp-Less 8-bit 1-MS/s Pipelined ADC in 90-nm CMOS Technology

Abbasizadeh¹,

Rikan²,

Lee³

et al. 2014

IEIE Transactions on Smart Processing and Computing

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This paper presents an 8-bit pipelined analog-to-digital converter. The supply voltage applied for comparators and other sub-blocks of the ADC were 0.7V and 0.5V, respectively. This low power ADC utilizes the capacitive charge pump technique combined with a source-follower and calibration to resolve the need for the opamp. The differential charge pump technique does not require any common mode feedback circuit. The entire structure of the ADC is based on fully dynamic circuits that enable the design of a very low power ADC. The ADC was designed to operate at 1MS/s in 90nm CMOS process, where simulated results using ADS2011 show the peak SNDR and SFDR of the ADC to be 47.8 dB (7.64 ENOB) and 59 dB respectively. The ADC consumes less than 1mW for all active dynamic and digital circuitries.

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A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification

Cited by 418 publications

References 21 publications

On Calibration Techniques for Pipelined ADCs

On Calibration Techniques for Pipelined ADCs

Design of a SoC for Intermediate Frequency Digital Receiver

A Low-Voltage Low-Power Opamp-Less 8-bit 1-MS/s Pipelined ADC in 90-nm CMOS Technology

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