A 12-bit 30MS/s SAR ADC with VCO-Based Comparator and Split-and-Recombination Redundancy for Bypass Logic

Chang, Sheng; Zhou, Xiong; Ding, Zhaoming; Li, Qiang

doi:10.1109/iscas.2019.8702448

Cited by 4 publications

(9 citation statements)

References 10 publications

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“…stands for the current bypass window size of W 4 , and its initial value is 1 LSB. If differential signals cannot cross zero (common-mode voltage), the bypass window is too small and this process of the bypass is wrong [17] . The cycle must be back to where the bypass begins and W 4 is updated.…”

Section: Operation Principlementioning

confidence: 99%

“…Apart from making decisions and employing the decisions to reduce the comparator noise [14−16] , a VCO-based comparator offers extra information, known as the number of oscillation cycles (NOC) [17] , to detect whether the input signal of the comparator is in the vicinity of common-mode voltage. This information can be utilized to trigger bypass logic, which avoids the use of additional comparators and reference.…”

Section: Introductionmentioning

confidence: 99%

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A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows

et al. 2020

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This paper proposes a technique that uses the number of oscillation cycles (NOC) of a VCO-based comparator to set multiple adaptive bypass windows in a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The analysis of the number of bit cycles, power and static performance shows that three adaptive bypass windows reduce power consumption, and decrease DNL and have similar INL, compared with the SAR ADC without bypass windows. In addition, a 1-bit split-and-recombination redundancy technique and a general bypass logic digital error correction method are proposed to address the settling issues and optimize the size of the bypass window. This design is implemented in 40 nm CMOS technology. The conversion frequency of the ADC reaches up to 30 MS/s. The ADC achieves an SFDR of 85.35 dB and 11.12-bit ENOB with Nyquist input, consuming 380 μW, down from 427 μW without multiple adaptive bypass windows, at a 1.1 V supply, resulting in a figure of merit (FoM) of 5.69 fJ/conversion-step.

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Section: Operation Principlementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows

et al. 2020

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“…Moreover, larger driving switches introduce more parasitic capacitance, which reduces the speed of the ADC. The redundancy can alleviate the settling error of a DAC [16][17][18][19][20][21][22][23][24][25][26][27][28]. The nonbinary redundancy [29] needs a complex digital control circuit and an extra an ROM.…”

Section: Introductionmentioning

confidence: 99%

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

Zheng

Ren

2022

Electronics

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This paper presents a 12-bit, 100 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on a bridge capacitor array with redundancy and non-linearity calibration. The differential non-linearity calibration method was proposed to compensate for the linearity, which is degraded by the parasitic capacitance of the bridge capacitor. To reduce the power dissipation and alleviate the settling error of the DAC capacitor array, a hybrid redundant scheme was proposed. A low-power, high-performance SAR ADC was implemented based on the proposed techniques. This SAR ADC prototype was implemented in 28 nm CMOS technology. Measurement results showed that the proposed SAR ADC could achieve a (signal-to-noise distortion ratio) SNDR of 61.46 dB and 58.82 dB at low and Nyquist input frequencies, respectively, resulting in figure of merits (FOMs) of 8.69 fJ/conversion and 11.8 fJ/conversion step, respectively. The SAR ADC core occupied an active area 0.0227 mm2.

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“…For traditional voltage-domain comparator, every 1-bit resolution improvement in signal-to-noise ratio (SNR) requires four times power consumption of the comparator, which results in less energy-efficient. To improve the energy-efficiency, time-domain comparators are developed [18][19][20]. The edge-pursuit comparator proposed in [18] achieves good energy-efficiency as well as design flexibilities in terms of the input referred noise and offset.…”

Section: Introductionmentioning

confidence: 99%

“…The edge-pursuit comparator proposed in [18] achieves good energy-efficiency as well as design flexibilities in terms of the input referred noise and offset. The VCO-based comparator in [19,20] employs the information provided by the comparator to achieve the meta-stability or adaptive bypassing window to improve the overall power-efficiency of SAR ADC.…”

Section: Introductionmentioning

confidence: 99%

A Time-Domain Comparator Based Skipping-Window SAR ADC

Xie¹,

Ren²,

Zhou³

et al. 2021

Computers, Materials &Amp; Continua

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This paper presents an energy efficient successive-approximation register (SAR) analog-to-digital converter (ADC) for low-power applications. To improve the overall energy-efficiency, a skipping-window technique is used to bypass corresponding conversion steps when the input falls in a window indicated by a time-domain comparator, which can provide not only the polarity of the input, but also the amount information of the input. The timedomain comparator, which is based on the edge pursing principle, consists of delay cells, two NAND gates, two D-flip-flop register-based phase detectors and a counter. The digital characteristic of the comparator makes the design more flexible, and the comparator can achieve noise and power optimization automatically by simply adjusting the delay cell number. An energy efficient digital-to-analog converter (DAC) control scheme suitable for the skipping window technique is also developed to reduce the switching energy during SAR conversion. Together with the skipping-window technique, the linearity and the power consumption of the SAR ADC are improved. The impact of different window sizes on comparison cycles, DAC switching energy and the overall energy efficiency is analyzed. Simulation results show that the proposed skipping-window technique can improve the overall energy-efficiency of the SAR ADC, as well as the linearity, and the optimized window size for the overall energy efficiency will vary with the DAC switching energy.

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A 12-bit 30MS/s SAR ADC with VCO-Based Comparator and Split-and-Recombination Redundancy for Bypass Logic

Cited by 4 publications

References 10 publications

A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows

A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

A Time-Domain Comparator Based Skipping-Window SAR ADC

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