A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET

Luu, Danny; Kull, Lukas; Toifl, Thomas; Menolfi, Christian; Brändli, Matthias; Francese, Pier Andrea; Morf, Thomas; Kossel, Marcel; Yueksel, Hazar; Cevrero, Alessandro; Özkaya, İlter; Huang, Qiuting

doi:10.1109/jssc.2018.2862890

Cited by 23 publications

(13 citation statements)

References 22 publications

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“…A servo-loop has been used, which senses the comparator output and feeds back to the input the opposite offset value until the comparator goes into a metastable state. For the designed V CM of 0.5 V, the 1-σ raw value for both [10,11,25,26] was larger than 11 mV, while it was 9.8 mV for the proposed design ( Figure 6a). After enabling the proposed calibration, the offset was improved to 0.69 mV, set by the designed C INT /C CAL ratio and noise, without compromising the rest of the specifications.…”

Section: (Mv)mentioning

confidence: 96%

“…The implemented self-calibrating comparator performance in terms of delay and noise has been characterized with extracted simulations and compared to the comparators from [10,11,25,26], scaled to 28 nm ( Figure 5). For the comparator delay, the Overdrive Recovery Test (ORT) [27,28] has been used, while the noise has been characterized with both pss + pnoise and transient simulations.…”

Section: Comparator Corementioning

confidence: 99%

“…For the comparator delay, the Overdrive Recovery Test (ORT) [27,28] has been used, while the noise has been characterized with both pss + pnoise and transient simulations. The operating conditions were V DD = 1.0 V and V CM = 0.5 V. The proposed design achieved more than 20% faster regeneration time for small inputs due to the increased gain in the signal path and showed a lower input dependency for a wide range of voltages compared to [10,11,25,26] (Figure 5a). To achieve similar regeneration times, the tail, as well as the latching transistors of the works in [10,11,25,26] had to be upscaled, whose combined contribution increased the total input-referred noise by more than 15% with respect to this design, as shown in Figure 5b.…”

Section: Comparator Corementioning

confidence: 99%

“…Comparator [10,25] Comparator [11,26] This comparator = 0.9 mV = 1.01 mV = 0.78 mV (b) Figure 5. Simulated delay versus ΔV IN for the same offset/noise (a) and cumulative noise distribution for similar delay (b) for [10,11,25,26] and the proposed design.…”

Section: (Mv)mentioning

confidence: 99%

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An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

et al. 2018

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This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less than 5% power overhead. Moreover, the implemented multi-stage topology significantly advances the state-of-the-art comparator performance, achieving the highest reported operating frequency, as well as the lowest delay slope and sensitivity to supply and common mode variations compared to existing works, with similar energy/comparison. This makes the proposed self-calibrating comparator an ideal candidate for high resolution (>10 b) multi-GHz Analog-to-Digital Converters (ADCs). The 28 nm bulk CMOS prototype measures an input-referred noise and calibrated offset of 0.82 mV and 0.99 mV, respectively clocked at 11 GHz, consuming only 0.89 mW from a 1 V supply, for an area of 0.00054 mm 2 , including calibration.

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Section: (Mv)mentioning

confidence: 96%

Section: Comparator Corementioning

confidence: 99%

Section: Comparator Corementioning

confidence: 99%

Section: (Mv)mentioning

confidence: 99%

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An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

et al. 2018

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“…Recently, high-resolution (>10 ENOB (Effective Number of Bits)) and high-speed (>150 MS/s) analog-to-digital converters (ADCs) with low power consumption have become an essential building block in modern wireless communication systems. Owing to the evolution of the CMOS process, the charge-redistribution successive-approximationregister (SAR) ADC is very attractive as a high-performance ADC [1][2][3][4][5]. However, the SAR ADC has a speed bottleneck due to the serial conversion mechanism, and it is difficult to have a high signal-to-noise ratio (SNR) due to the comparator noise.…”

Section: Introductionmentioning

confidence: 99%

A Single-Amplifier Dual-Residue Pipelined-SAR ADC

Seo

2021

Electronics

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This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm2. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.

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Design of an auto adaption unit for reconfigurable analog to digital converters

Kakarla

Alagirisamy

2021

Int J Speech Technol

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A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET

Cited by 23 publications

References 22 publications

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

A Single-Amplifier Dual-Residue Pipelined-SAR ADC

Design of an auto adaption unit for reconfigurable analog to digital converters

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