A 12 bit 2.9 GS/s DAC With IM3 $ ≪ -$60 dBc Beyond 1 GHz in 65 nm CMOS

Lin, Chi‐Hung; Goes, F.M.I. van der; Westra, J.G.; Mulder, J.A.; Lin, Yu Chang; Arslan, E.; Ayranci, E.; Liu, Xiaodong; Bult, Klaas

doi:10.1109/jssc.2009.2032624

Cited by 172 publications

(105 citation statements)

References 13 publications

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“…However, this requires a DAC core which is capable of producing at least 8 GSps for a 4 GHz RF output, which is a very high speed for the required linearity. Known problems with high linearity DACs at high frequency are the data-dependent output impedance [28], timing errors due to mismatch [27] and inter-symbol-interference.…”

Section: Sequence Of Operationsmentioning

confidence: 99%

Classification for synthesis of high spectral purity current-steering mixing-DAC architectures

Bechthum

Radulov

Briaire³

et al. 2015

Analog Integr Circ Sig Process

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This paper proposes a classification of Mixing-DAC architectures, focusing on spectral purity. Based on literature research, analysis and simulations, the proposed classification shows the impact of architectural choices on the output spectral purity. To concretize the classification and validate the analysis, a number of specific Mixing-DAC architectures are synthesized, discussed and simulated. Given the proposed classification, a set of optimal architectural choices lead to a strong architecture candidate for achieving high spectral purity at high signal frequencies, i.e. SFDR [ 80 dBc at f OUT = 4 GHz for current and future multicarrier GSM applications. The main characteristics of this architecture are: Cartesian signaling, local Gilbert-cell mixing and a fully differential implementation.

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Section: Sequence Of Operationsmentioning

confidence: 99%

Classification for synthesis of high spectral purity current-steering mixing-DAC architectures

Bechthum

Radulov

Briaire³

et al. 2015

Analog Integr Circ Sig Process

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“…The non-linearities in the DAC are one of the critical bottlenecks for the overall performance of the ADC. In order to cope with these non-linearities, various dynamic element matching (DEM) techniques have been used, for example, [76][77][78][79][80][81][82][83][84][85][86][87][88][89]. A disadvantage of the DEM is that size and power consumption grow exponentially with the increased word length and higher resolution of the digital feedback signal.…”

Section: Motivationmentioning

confidence: 99%

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

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Papers A and C are reprinted with permission from IEEE.Cover figure is an illustration of the digital cascaded error-feedback modulator.Printed by LiU-Tryck, Linköping, Sweden 2014 To my parents and teachers AbstractA number of state-of-the-art low power consuming digital delta-sigma modulator (∆Σ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ∆Σ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ∆Σ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.Further on, it is described that the architectural properties of a unit elementbased DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.All of the designs are subjected to rigorous analysis and are described mathev vi Abstract matically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry. Populärvetenskaplig sammanfattning vii viiiPopulärvetenskaplig sammanfattning I denna avhandling presenteras e...

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“…In [34,35] a solution is proposed to eliminate the error due to the code-dependent capacitance seen at the output terminals of the DAC. This solution is shown in figure 2-4.…”

Section: Extra Cascodes With Bleeding Current Sourcesmentioning

confidence: 99%

“…[22] achieves a better SFDR, but this does utilize return-tozero, which as discussed in section 2.3.2 also has its downsides. While [15] and [34] have a higher sampling rate and output swing, this does come at the cost of a much higher required supply, higher power consumption and a significantly larger core size. [55] is comparable in supply voltage and power consumption, while additionally only requiring a very small area.…”

Section: Hd3mentioning

confidence: 99%

“…The interleaving architecture inherently suppresses the propagation of switching related errors to the DAC output which lowers the demand on generation of the switch signals. Both current-mode logic (CML) drivers and CMOS circuitry can be used to drive the quad-switches [34,55]; both having specific advantages and disadvantages. Quad-switching combined with interleaving removes the need for most of the CML advantages, and using CML in combination with quadswitching is more complicated than using CMOS drivers.…”

Section: Switch Drivers and Signal Generationmentioning

confidence: 99%

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Time-interleaved high speed D/A converters

Olieman¹

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A 12 bit 2.9 GS/s DAC With IM3 $ ≪ -$60 dBc Beyond 1 GHz in 65 nm CMOS

Cited by 172 publications

References 13 publications

Classification for synthesis of high spectral purity current-steering mixing-DAC architectures

Classification for synthesis of high spectral purity current-steering mixing-DAC architectures

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Time-interleaved high speed D/A converters

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