A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector

Yuan, Zhijun; Xu, Benwei; Chiu, Yun

doi:10.1109/jssc.2014.2384025

Cited by 111 publications

(58 citation statements)

References 22 publications

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“…In recent years, with the improvement of CMOS technology, successive approximation register (SAR) analog-todigital converters ADCs have been able to achieve sampling rates of several hundreds of MS/s with high power efficiency and small area [1,2,3,4,5,6,7,8,9,10]. Meanwhile, 8 to 12-bit SAR ADCs could reach sampling rates of hundreds or thousands MS/s and provide compact area and outstanding power efficiency [11,12,13,14,15,16,17,18,19,20,21,22].…”

Section: Introductionmentioning

confidence: 99%

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

Pu-Jie

et al. 2019

IEICE Electron. Express

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A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique is proposed. With the variation of input signals, the parasitic capacitance variation of sampling switch is reduced and the total parasitic capacitance is also depressed. Moreover, with substrate boost technique, the on-impedance of sampling switch would decrease. To demonstrate the proposed technique, a design of 12bit 100-MS/s SAR ADC is fabricated in 40-nm CMOS technology, consuming 2 mW from 1 V power supply with a SNDR >65 dB and SFDR >83 dB. The proposed ADC core occupies an active area of 0.02 mm 2 , and the corresponding FoM is 13.8 fJ/conversion-step with Nyquist frequency.

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Section: Introductionmentioning

confidence: 99%

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

Pu-Jie

et al. 2019

IEICE Electron. Express

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“…Recently, there are quite a few low-power or high-performance SAR ADC circuits reported in literature [1][2][3][4][5][6][7][8][9][10]. Typically, SAR ADCs implement the binary search algorithm and require N conversion cycles to generate an N-bit digital output.…”

Section: Introductionmentioning

confidence: 99%

“…Several recent ADC circuits exploit this opportunity in different ways. The designs in [8,9] take advantage of timing information to detect comparator metastability, subsequently improving ADC resolution or accelerating the conversion process. The proximity detector in [9] also relies on comparator timing information to detect when noise signal can be injected for background calibration.…”

Section: Introductionmentioning

confidence: 99%

“…The designs in [8,9] take advantage of timing information to detect comparator metastability, subsequently improving ADC resolution or accelerating the conversion process. The proximity detector in [9] also relies on comparator timing information to detect when noise signal can be injected for background calibration. According to comparator timing information, the ternary SAR ADC in [10] divides the search space into three sub regions similar to that in pipelined ADCs with 1.5-bits per stage.…”

Section: Introductionmentioning

confidence: 99%

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A novel time and voltage based SAR ADC design with self-learning technique

Nagabhushana

Wang

2016

Proceedings of the 53rd Annual Design Automation Conference

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This paper presents a novel time and voltage based technique for successive approximation register (SAR) analogto-digital converter (ADC) to improve the conversion speed. By taking advantage of the fact that at low supply voltage there will be a significant difference in comparator decision time for different input voltages, the proposed technique creates multiple auxiliary voltage levels for comparison and hence eliminates the need of additional comparators for acceleration as compared with the existing methods. In addition, a digital self-learning module is also presented, which calculates the uncertainty window required for bound update in the proposed method and thus adjusts to different process corners. To validate these concepts, a 10-bit SAR ADC is designed in 130nm CMOS process with 0.5V power supply voltage. The circuit operates in both conventional and proposed modes. Simulations show that the largest number of conversion cycles is 7, hence resulting in an acceleration of 30% over the conventional scheme, while the average number of cycles is 5.58. Simulation results also demonstrate that the proposed method does not affect accuracy. Both ADC operation modes achieve SNDR (signal-tonoise distortion ratio) of 59dB, corresponding to an ENOB (effective number of bits) of 9.5-bits.

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“…To achieve the required noise level while still saving power, several techniques have been proposed. A two-stage pipelined SAR ADC [6], [7], [8], [9], [10] can relax the comparator noise by introducing a low-noise amplifier between the two stages. Nonetheless, the effort to design a low-power amplifier and to overcome the induced errors (e.g., gain error, offset error) is not trivial.…”

mentioning

confidence: 99%

A 46 $\mu \text{W}$ 13 b 6.4 MS/s SAR ADC With Background Mismatch and Offset Calibration

Ding

Harpe

Liu

et al. 2017

IEEE J. Solid-State Circuits

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A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector

Cited by 111 publications

References 22 publications

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

A novel time and voltage based SAR ADC design with self-learning technique

A 46 $\mu \text{W}$ 13 b 6.4 MS/s SAR ADC With Background Mismatch and Offset Calibration

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