A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology

In this paper, a time-interleaved 10-GS/s 8-bit analog-to-digital converter (ADC) fabricated in 0.18 µm SiGe BiCMOS technology has been demonstrated. A 4 × 4 input multiplexer with good isolation and wide input bandwidth is proposed, which enables the ADC to support 1/2/4-channel sampling modes. In the track-and-hold (THA) stage, a switched emitter follower (SEF) topology with delayed dummy clock is introduced to minimize the overshoot effect of the SEF output. The ADC achieves spurious free dynamic range (SFDR) > 52 dBc and effective number of bits (ENOB) > 6.8 in low input frequencies. The analog input bandwidth is 5.6 GHz.

Section: Introductionmentioning

confidence: 99%

A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS

Liu

Zhou

et al. 2019

“…As wireless communication technology is advancing, the requirements of accuracy and speed for Analog-to-Digital Converters (ADCs) are increasing. Compared with other architectures, a pipelined ADC is more suitable for highspeed and high-resolution applications like the wideband receiver system [1,2,3]. A SHA-less architecture with an input buffer has been widely employed to design highspeed pipelined ADCs [4,5].…”

Section: Introductionmentioning

confidence: 99%

“…Implementation of each stages Simplified schematic of the buffer proposed in this paperIEICE Electronics Express, Vol.16, No.11,[1][2][3][4][5] …”

mentioning

confidence: 99%

A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS

Chen¹,

Shen³

et al. 2019

In this paper, a 14 bit 500 MS/s SHA-less pipelined Analog-to-Digital Converter (ADC) realized in 40 nm CMOS technology is presented. A 2.5 V powered buffer that exhibits a comprehensive bootstrap architecture is proposed to achieve the trade-off between linearity and power consumption. Besides, the high-voltage-thin-oxide-device design is incorporated to further improve the linearity. In the meantime, an improved supply voltage domain arrangement is proposed to achieve a single power design and improve structural power efficiency. The measured Signal-to-Noise-and-Distortion-Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) are 71 dB and 79 dBc at 120.2 MHz input signal under 500 MS/s. The ADC occupies an active area of 0.4 mm 2 and consumes a total power of 300 mW.

“…In recent years, the study of analog-to-digital converters (ADC) with resolutions higher than 8 b and sample rates over gigahertz has enabled the use of softwaredefined radios to be applied in more applications [1,2]. In high-speed applications, the flash ADCs enjoy exceptional advantages.…”

Section: Introductionmentioning

confidence: 99%

A 1 GS/s 12-bit pipelined folding ADC with a novel encoding algorithm

Liu

Zhou

et al. 2019

In this paper, a 1-GS/s 12-bit pipelined folding analog-to-digital converter (ADC) fabricated in 40 nm CMOS technology is presented. A new encoding algorithm based on distributed quantization is proposed to simplify the quantization process of the structure with odd folding factor and reduce the hardware consumption of the circuit. The ADC achieves spurious free dynamic range (SFDR) > 72 dB and signal-to-noise and distortion ratio (SNDR) > 57 dB in low input frequencies.