A 12.7 Mchip/s all-digital BPSK direct sequence spread-spectrum IF transceiver in 1.2 μm CMOS

Chien, Charles; Yang, P.T.; Cohen, E.; Jain, Rajeev; Samueli, H.

doi:10.1109/isscc.1994.344741

Cited by 9 publications

(7 citation statements)

References 4 publications

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“…Table 3 reports the run-time and the maximum delay by HSPICE simulations of six routed nets in an Intel microprocessor design [5]. 3 The experimental results show that comparable maximum delay is achieved by our method with significantly shorter run-time. Note that the wires in the six nets are divided into 100µm segments before we apply the two algorithms.…”

Section: Resultsmentioning

confidence: 96%

“…We apply the SBWS algorithms to the clock nets in a spread spectrum IF transceiver chip developed for wireless adaptive mobile information system (WAMIS) project at UCLA [3]. The integrated single-chip transceiver chip has a die size of 7:9 10:0mm 2 , is designed under 1:2µm 2-level metal SCMOS technology, and has a total power dissipation of 1:1W.…”

Section: Resultsmentioning

confidence: 99%

“…The relation leads to a polynomial time algorithm for computing the lower and upper bounds of the optimal SBWS solutions, which enables an efficient optimal algorithm for computing optimal SBWS solutions. We have applied the SBWS algorithms to the clock nets in a spread spectrum IF transceiver chip designed at UCLA for wireless multimedia information systems [3]. HSPICE simulations show that our algorithms can reduce power by a factor of 2:6X when compared to the manual layout of the clock nets in the original chip.…”

Section: Introductionmentioning

confidence: 99%

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Simultaneous buffer and wire sizing for performance and power optimization

Cong¹,

Koh²,

Leung³

Proceedings of 1996 International Symposium on Low Power Electronics and Design

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In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions. This relation leads to a polynomial time algorithm for computing the lower and upper bounds of the optimal SBWS solutions, which enables an efficient optimal algorithm for computing optimal SBWS solutions. We have applied the SBWS algorithms to the clock nets in a spread spectrum IF transceiver chip and HSPICE simulations show that our algorithms can reduce skew and power by a factor of 3:5X and 2:6X, respectively, when compared to the manual layout of the clock nets in the original chip.

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Section: Resultsmentioning

confidence: 96%

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Simultaneous buffer and wire sizing for performance and power optimization

Cong¹,

Koh²,

Leung³

Proceedings of 1996 International Symposium on Low Power Electronics and Design

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“…Let x be the transistor width, rd; c g ; c s and cd can be written as the following: rd = rd0=x (1) cg = cg0 x + cg1 (2) cs = cs0 x + cs1 (3) cd = cd0 x + cd1 (4) where cg0; c s 0 and cd0, a s w ell as cg1; c s 1 and cd1 are constants determined by the technology. In addition, rd0 is the unit eective resistance as dened in the following: assuming an n-type transistor is driven by a rising input.…”

Section: Formulations 21 Delay Model For Transistors and Interconnectsmentioning

confidence: 99%

“…A spread spectrum IF transceiver chip is designed recently [4] and the 1.2 m 2-layer metal SCMOS technology is used. There are two clock nets, named DCLK and CLK.…”

Section: Simultaneous Driver/buer and Wire Sizingmentioning

confidence: 99%

An efficient approach to simultaneous transistor and interconnect sizing

Cong¹,

He²

Proceedings of International Conference on Computer Aided Design

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In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We dene a class of optimization problems as CH-posynomial programs and reveal a general dominance property for all CH-posynomial programs (Theorem 1). We show that the STIS problems under a number of transistor delay models are CH-posynomial programs and propose an ecient and near-optimal STIS algorithm based on the dominance property. When used to solve the simultaneous driver/buer and wire sizing problem for real designs, it reduces the maximum delay b y u p t o 16.1%, and more signicantly, reduces the power consumption by a factor of 1.63x, when compared with the original designs. When used to solve the transistor sizing problem, it achieves a smooth area-delay trade-o. Moreover, the algorithm optimizes a clock net of 367 drivers/buers and 59304m-long wire in 120 seconds, and a 32bit adder with 1,026 transistors in 66 seconds on a SPARC-5 workstation.

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Channel coding for a frequency-hopped wireless transceiver

Lin

Pottie

1994

Information Theory and Applications

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A 12.7 Mchip/s all-digital BPSK direct sequence spread-spectrum IF transceiver in 1.2 μm CMOS

Cited by 9 publications

References 4 publications

Simultaneous buffer and wire sizing for performance and power optimization

Simultaneous buffer and wire sizing for performance and power optimization

An efficient approach to simultaneous transistor and interconnect sizing

Channel coding for a frequency-hopped wireless transceiver

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