A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC

Li, Manxin; Chen, Yongzhen; Ye, Fan; Ren, Junyan

doi:10.1109/iscas.2018.8351387

Cited by 4 publications

(2 citation statements)

References 5 publications

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“…The successive approximation register (SAR) analog-to-digital converter (ADC) is very popular because it can achieve low power and high performance at 100 MS/s with 10 to 13 bits [1][2][3][4][5][6][7][8][9][10]. With the feature sizes of CMOS devices scaled down, the power supply voltage becomes lower and lower, which is not conducive to analog circuits such as highperformance operational amplifiers as the low power supply voltage limits the output swing and gain of the amplifier.…”

Section: Introductionmentioning

confidence: 99%

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

Zheng

Ren

2022

Electronics

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This paper presents a 12-bit, 100 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on a bridge capacitor array with redundancy and non-linearity calibration. The differential non-linearity calibration method was proposed to compensate for the linearity, which is degraded by the parasitic capacitance of the bridge capacitor. To reduce the power dissipation and alleviate the settling error of the DAC capacitor array, a hybrid redundant scheme was proposed. A low-power, high-performance SAR ADC was implemented based on the proposed techniques. This SAR ADC prototype was implemented in 28 nm CMOS technology. Measurement results showed that the proposed SAR ADC could achieve a (signal-to-noise distortion ratio) SNDR of 61.46 dB and 58.82 dB at low and Nyquist input frequencies, respectively, resulting in figure of merits (FOMs) of 8.69 fJ/conversion and 11.8 fJ/conversion step, respectively. The SAR ADC core occupied an active area 0.0227 mm2.

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Section: Introductionmentioning

confidence: 99%

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

Zheng

Ren

2022

Electronics

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“…Shubin Liu et al adopted the output offset storage method to improve linearity and the novel switching scheme to obtain power efficiency [5]. Moreover, non-binary search with redundancy solution is often utilized to improve the capacitor digital-to-analog converter (CDAC) settling and reduce reference current [6][7][8][9][10]. From these works, it can be found that reducing the number of capacitors is the foundation of power-efficient SAR ADC design.…”

Section: Introductionmentioning

confidence: 99%

A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

Tang

Shu

et al. 2021

Electronics

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This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm2. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/−0.44 and +0.48/−0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step.

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A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling Period

Zhang

Cao

et al. 2019

2019 IEEE 13th International Conference on ASIC (ASICON)

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A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC

Cited by 4 publications

References 5 publications

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling Period

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