A 10 bit low-power CMOS D/A converter with on-chip gain error compensation

Design techniques for high-performance current-steering digital-to-analog converters

“…The well-known row-column switching scheme is commonly used in a heuristic attempt to optimize the switching sequence [5], [13], [14], [17], [47], [48]. In this scheme, the spatial gradient are averaged in two directions as shown in Figure 3.3 and the sequences for row and column selection are optimized independently.…”