A 10-bit 1.2 GS/s 45 mW time-interleaved SAR ADC with background calibration

Abstract

A 10-bit 1.2GS/s power efficient time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) is present in this paper. Substrate bias effect depression and output resistance stabilization techniques are provided to enhance the linearity of input buffer. Further, meta-stability restrained trigger comparator is used to enhance the ENOB (effective number of bits) of SAR ADC. Additionally, a digital background calibration technique is proposed to suppress the inter-channel gain, offset and timing skew mismatches. To demonstrate the proposed techniques, a design of time-interleaved SAR ADC is fabricated in 55-nm CMOS technology, consuming 45mW from 1.2V power supply with a SNDR of 50dB and SFDR of 60dB. The proposed ADC core occupies an active area of 0.84mm 2 , and the corresponding FoM is 145 fJ/conversion-step with Nyquist rate. Keywords: Analog-to-digital converter (ADC), Time-interleaved ADC, successive-approximation-register (SAR) ADC, Meta-stability restrained, High-linearity, Background calibration. Classification: Analog integrated circuits [11] Sunghyuk Lee, Anantha P. Chandrakasan and Hae-Seung Lee, "A 1GS/s 10b 18.9mW time-Interleaved SAR ADC with background timing skew calibration", IEEE J.

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

“…Based on high performance SAR ADC, time-interleaved SAR ADCs (TI SAR ADC) are superior in aspects of highly scalable and power efficiency to advanced CMOS technology. Several calibration techniques are provided in [23,24,25,26,27,28] to correct the non-ideal errors produced by channel mismatches in time-interleaved SAR ADC. For every type of SAR ADCs, linearity of sampling switch is the bottleneck for system linearity, the parasitic diodes of source/drain to substrate exist in the sampling switch.…”