A 10-b 20-Msample/s analog-to-digital converter

Lewis, S.H.; Fetterman, H.S.; Gross, G.F.; Ramachandran, R.; Viswanathan, T.R.

doi:10.1109/4.121557

Cited by 431 publications

(168 citation statements)

References 13 publications

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“…General diagram of Analog-to-Digital Converter (ADC) pipeline 5 bits is shown in Figure 1, and further in references (Lewis et al, 1992;Cho & Gray, 1994;Brandt & Lutsky, 1999).…”

Section: Adc Pipeline and Operational Modementioning

confidence: 99%

Impact of Injected Charges, Clock Noise and Operational Amplifier Imperfections on the Sample and Hold (SH) Overall Performance

Ndiaye¹,

Dzahini²,

Ndiaye³

et al. 2012

APR

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The growing use of digital processing in analog environments underlines the importance of Analog Digital Converter (ADC) occurrence in circuitry. The quality and reliability of the conversion are closely linked to the Sample and Hold (SH) performance. Actually SH is a key component in the Analog/Digital chain. The Operational Amplifier being at the heart of the SH influences its output and subsequently impacts the reliability and quality of the conversion. In this paper we present the impact of both Operational Amplifier intrinsic characteristics and external factors such as injected charges, and clock noise on the SH overall performance. We limit our consideration to the offset and parasite capacities as the only relevant Operational Amplifier intrinsic characteristics. We'll introduce the Operational Amplifier and SH functional characteristics then address the impact of each of these parameters on the SH output which the ADC works on. A behavioral description of the Operational Amplifier based on the Verilog-A language under Cadence approach is used. Furthermore a behavioral/analog mixed description is considered for the SH: the Operational Amplifier described behaviorally in Verilog-A is associated to analog components in Cadence libraries and CMOS switches act as SH. However this simplistic approach doesn't reflect all the challenges involved, because it is not enough to connect a SH to ADC to flawlessly digitalize an analog signal. The SH architecture and the Operational Amplifier characteristics play also a role for a reliable sampling and therefore a good quality conversion prospect.In this study the SH performance is evaluated through its non-linearity which in turn determines the sampling accuracy a key factor for a conversion. This study is as shown that small amplitude signals are more sensible to sampling errors related to Operational Amplifier offset. Furthermore the stray capacities attenuate the SH signal output. The injected charges and the clocknoise as strongly interrelated contribute to the non-linearity of the conversion chain.

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“…General diagram of Analog-to-Digital Converter (ADC) pipeline 5 bits is shown in Figure 1, and further in references (Lewis et al, 1992;Cho & Gray, 1994;Brandt & Lutsky, 1999).…”

Section: Adc Pipeline and Operational Modementioning

confidence: 99%

Impact of Injected Charges, Clock Noise and Operational Amplifier Imperfections on the Sample and Hold (SH) Overall Performance

Ndiaye¹,

Dzahini²,

Ndiaye³

et al. 2012

APR

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“…This widely-employed error correction method is referred to as redundant signed digit (RSD) correction, and was developed for algorithmic ADCs in [62] and [63] and utilized in pipelined ADC in [64]. Other related methods have also been used (e.g.…”

Section: Rsd Correctionmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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“…Recently, with the improvement of modern process technology, research on high-speed highresolution ADCs for communication systems has become one of the trends. These types of ADCs need to have an accuracy of over 14 bits and sample rate of over 100 MHz [1,2] and the pipelined ADCs are an acceptable architecture due to its characteristics [3]. Additionally, standard CMOS process has the advantages of lower cost and power consumption over expensive BiCMOS technology.…”

Section: Introductionmentioning

confidence: 99%

A 14-bit 100 MS/s SHA-less pipelined ADC with 89 dB SFDR and 74.5 dB SNR

Wang¹,

Fan²,

Pan³

et al. 2015

IEICE Electron. Express

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In this paper, a 14-bit 100 MS/s pipelined Analog-to-Digital Converter (ADC) in 0.18 µm CMOS process with a SHA-less frontend is demonstrated. The methods of clock adjustment and voltage reference separation are proposed to speed up the settling of residue amplifier. Meanwhile, an effective digital background calibration mechanism is employed in the first two stages to correct both capacitor mismatches and linear gain error of residue amplifier. After calibration, the presented ADC achieves an spuriousfree dynamic range (SFDR) of 89 dB, a signal-to-noise ratio (SNR) of 74.5 dB and a signal-to-noise and distortion ratio (SNDR) of 74.2 dB with a 30.2 MHz input signal, while keeping over 71.6 dB SNR and 70.2 dB SFDR with input signals up to 200 MHz. The chip consumes 440 mW from a 1.8 V supply and occupies an area of 4 × 2.6 mm 2 .

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A 10-b 20-Msample/s analog-to-digital converter

Cited by 431 publications

References 13 publications

Impact of Injected Charges, Clock Noise and Operational Amplifier Imperfections on the Sample and Hold (SH) Overall Performance

Impact of Injected Charges, Clock Noise and Operational Amplifier Imperfections on the Sample and Hold (SH) Overall Performance

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

A 14-bit 100 MS/s SHA-less pipelined ADC with 89 dB SFDR and 74.5 dB SNR

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