A 10-b 15-MHz CMOS recycling two-step A/D converter

Song, Bang‐Sup; Lee, S.-H.; Tompsett, M.F.

doi:10.1109/4.62176

Cited by 131 publications

(16 citation statements)

References 18 publications

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“…Similar ideas are also applied effectively to pipelined ADCs [71][72][73][74][75][76][77][78], two-step ADCs [79][80][81][82], and algorithmic (or cyclic) ADCs [83]. The radixes used include 1.8 [27], [28], [70], 1.85 [26], 1.86 [42], [60], and 1.93 [75].…”

Section: B Circuit Implementationmentioning

confidence: 98%

Non-binary Successive Approximation Analog-to-Digital Converters: A Survey

Waho

2014

2014 IEEE 44th International Symposium on Multiple-Valued Logic

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Low-power successive-approximation (SA) analogto-digital converters (ADCs) are attracting increasing attention these days in biomedical and sensor network applications. The binary search algorithm is one of the basic idea behind how they obtain a binary code representing an analog input. In practice, the imperfectness of analog circuit elements sometimes results in decision errors and decreases the resolution of A/D conversion. Thus, making accurate decisions using imperfect elements is a big challenge. This paper surveys one solution known as non-binary SA with redundancy as well as related topics and its application to state-of-the-art SA ADCs.

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Section: B Circuit Implementationmentioning

confidence: 98%

Non-binary Successive Approximation Analog-to-Digital Converters: A Survey

Waho

2014

2014 IEEE 44th International Symposium on Multiple-Valued Logic

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“…Resolution up to 14 bits has been reported without calibration, and the conversion rate of 1 GS/s with 11-bit resolution has been achieved with time interleaving [1]- [4]. Two key elements that enable this wide range of performance are digital error correction with redundancy [1] and capacitor-array multiplying digital-to-analog converter (MDAC) [5]. The accuracy of the residue generated by an MDAC depends on the settling accuracy of the operational amplifier (opamp) and the capacitor matching in the reconstruction DAC.…”

Section: Introductionmentioning

confidence: 99%

A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse

Ryu

Song

Bacrania

2007

IEEE J. Solid-State Circuits

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Power and area saving concepts such as operational amplifier (opamp) bias current reuse and capacitive level shifting are used to lower the analog power of a 10-bit pipelined analog-to-digital converter (ADC) to 220 W/MHz. Since a dual-input bias current reusing opamp performs as two opamps, the opamp summing nodes can be reset in every clock cycle. By using only N-channel MOS (NMOS) input stages, the capacitive level shifter simplifies the gain-boosting amplifier design and enables fast opamp settling with low power-consumption. The prototype achieves 9.2/8.8 effective number of bits (ENOB) for 1-and 20-MHz inputs at 50 MS/s. The ADC works within the temperature range of 0 to 85 C and the supply voltage from 1.62 to 1.96 V with little measured loss in the ENOB. The chip consumes 18 mW (11 mW for the analog portion of the ADC and 7 mW for the rest including buffers) at 1.8 V, and the active area occupies 1 1 1 3 mm 2 using a 0.18-m complementary metal oxide semiconductor (CMOS) process.Index Terms-Capacitor-array multiplying digital-to-analog converter (MDAC), digital-to-analog converter (DAC), low-power technique, opamp-sharing, pipelined analog-to-digital converter (ADC), switched-opamp.

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“…Separate power and ground are usedto the analog part of the chip to isolate the more sensitive analog circuitry from the digital switching noise. The comparator is a track-and-latch type [4]. The most critical performance limiting factor has been found to be the equivalent noise at the comparator input.…”

Section: Resultsmentioning

confidence: 99%

Integrating data converters for picoampere currents from electrochemical transducers

Breten

Lehmann

Braun³

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No

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This paper describes a current mode A D converter designed for a maximum input current range of 5nA and a resolution of the order of IPA. The converter is designed for a potentiostat for amperometric chemical sensors and provides a constant polarization voltage for the measuring electrode. A prototype chip using the dual slope conversion method has been fabricated in a 0.7pm CMOS process. Experimental results from this converter are reported. Design problems and limitations of the converter are discussed and a new conversion technique providing a larger dynamic range and easy calibration is proposed.

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A 10-b 15-MHz CMOS recycling two-step A/D converter

Cited by 131 publications

References 18 publications

Non-binary Successive Approximation Analog-to-Digital Converters: A Survey

Non-binary Successive Approximation Analog-to-Digital Converters: A Survey

A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse

Integrating data converters for picoampere currents from electrochemical transducers

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