A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse

Ryu, Seung‐Tak; Song, Bang-Sun; Bacrania, K.

doi:10.1109/jssc.2006.891718

Cited by 73 publications

(20 citation statements)

References 20 publications

(18 reference statements)

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“…5, during when a differential input of , with a common-mode of and a common-mode offset of is sampled, the charge sampled on node during is given by (5) (6) Similarly, during the charge sampled on is given by…”

Section: Appendixmentioning

confidence: 99%

A Low-Power Capacitive Charge Pump Based Pipelined ADC

Ahmed

Mulder²,

Johns

2010

IEEE J. Solid-State Circuits

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Abstract-A low-power pipelined ADC topology is presented which uses capacitive charge pumps, source-followers, and digital calibration to eliminate the need for power-hungry opamps to achieve good linearity in a pipelined ADC. The differential charge pump technique achieves 10-bit linearity, and does not require an explicit common-mode-feedback circuit. The ADC was designed to operate at 50 MS/s in a 1.8 V, 0.18 m CMOS process, where measured results show the peak SNDR and SFDR of the ADC to be 58.2 dB (9.4 ENOB), and 66 dB respectively. The ADC consumes 3.9 mW for all active circuitry and 6 mW for all clocking and digital circuits.

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Section: Appendixmentioning

confidence: 99%

A Low-Power Capacitive Charge Pump Based Pipelined ADC

Ahmed

Mulder²,

Johns

2010

IEEE J. Solid-State Circuits

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“…However, the op-amp sharing technique may degrade signal slewing and settling behaviors and increase layout complexity due to the required extra switches and the related parasitic components. Moreover, since op-amps are not reset, the offset voltages of the op-amps cannot be eliminated [11].…”

Section: Power Reduction Techniques For Sha and Mdacmentioning

confidence: 99%

A 12 b 8 kS/s 16 μW 0.35 μm CMOS algorithmic ADC for sensor interface in ubiquitous environments

Kim

Lee

2009

Analog Integr Circ Sig Process

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This work proposes a 12 b 8 kS/s ultra-lowpower CMOS algorithmic analog-to-digital converter (ADC) for sensor interface applications such as accelerometers and gyro sensors requiring high-resolution, lowpower, and small size simultaneously. The proposed ADC employs switched-bias power reduction and bias sharing circuits to minimize chip area and power dissipation. A signal-insensitive all directionally symmetric layout technique based on a double-poly CMOS process reduces capacitor mismatch in the multiplying D/A converter for 12 b-level high accuracy without additional conventional calibration schemes. Two independently generated currents with the same negative temperature coefficient are subtracted from each other to implement temperature-and supply-insensitive current and voltage references on-chip. The prototype ADC in a 0.35 lm 2P4M CMOS technology demonstrates a measured differential non-linearity and integral non-linearity within 0.15 and 0.56 LSB at 12 b and shows a maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range of 68 and 77 dB at 8 kS/s, respectively. The ADC with an active die area of 0.70 mm 2 consumes 16 lW at 8 kS/s and 2.5 V.

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“…Since reducing the power consumption is an important challenge for Systems-on-Chip (SoC) implementation, different power reduction techniques suitable for pipeline data converters have been proposed, such as, opamp sharing [3,4], S&H removal [5,6], switched-opamp techniques [7,8] pseudo-differential architectures [9] or digital calibration [10,11]. However, power consumption benefits yielded by these techniques are not for free and they involved long design cycles and extra development costs.…”

Section: Introductionmentioning

confidence: 99%

A 1.2 V 10-bit 60-MS/s 23 mW CMOS pipeline ADC with 0.67 pJ/conversion-step and on-chip reference voltages generator

Ruiz-Amaya

Delgado‐Restituto

Rodríguez-Vázquez

2011

Analog Integr Circ Sig Process

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A 1.2 V 10-bit 60 MS/s pipeline Analog-toDigital Converter (ADC), fabricated in a 130 nm CMOS technology, is presented. The prototype is composed by five 3-bit pipeline stages and a Sample and Hold (S&H) circuit at the front. Two-stage Miller-compensated Operational Transconductance Amplifiers (OTAs), offset-compensated comparators and bootstrapping sampling switches have been used due to the low voltage supply requirements. Special attention has been paid to the reduction of the power consumption using a thorough design methodology. The converter only consumes 23 mW including on-chip reference voltages and bias current generators. The differential and integral nonlinearity of the ADC are below 0.60 and 0.61 LSBs, respectively. The pipeline converter achieves an effective resolution above 9 bits along the Nyquist bandwidth, and obtains 0.67 pJ energy consumption per conversion, making it one of the most energyefficient 10-bit video-rate pipeline ADC reported to date.

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A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse

Cited by 73 publications

References 20 publications

A Low-Power Capacitive Charge Pump Based Pipelined ADC

A Low-Power Capacitive Charge Pump Based Pipelined ADC

A 12 b 8 kS/s 16 μW 0.35 μm CMOS algorithmic ADC for sensor interface in ubiquitous environments

A 1.2 V 10-bit 60-MS/s 23 mW CMOS pipeline ADC with 0.67 pJ/conversion-step and on-chip reference voltages generator

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