A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS

Nazemi, Ali; Grace, C.; Lewyn, L.L.; Kobeissy, B.; Agazzi, O.E.; Voois, P.; Abidin, C.; Eaton, Gareth R.; Kargar, Mahyar; Márquez, Carlos; Ramprasad, S.; Bollo, F.; Posse, V.; Wang, S.; Asmanis, G.

doi:10.1109/vlsic.2008.4585935

Cited by 47 publications

(12 citation statements)

References 4 publications

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“…The SAR-type front-end ADCs take advantage of the low power consumption of a single SAR ADC. Since a SAR ADC consumes extremely low power, large number of ADCs (e.g., [8][9][10][11][12][13][14][15][16] can be timeinterleaved to achieve high aggregate sampling rate. To minimize the impact of phase mismatch between the sampling clocks and maximize the input bandwidth a master-slave T&H structure can be employed.…”

Section: Discussionmentioning

confidence: 99%

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ADC-Based Backplane Receivers: Motivations, Issues and Future

Chung¹

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The analog-to-digital-converter-based (ADCbased) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both frontend ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using systemlevel models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

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Section: Discussionmentioning

confidence: 99%

“…Meanwhile, to meet the tight power budgets of the backplane link system, power consumption of the front-end ADC should be minimized. Unfortunately, designing a high-speed ADC consuming low power is non-trivial [7,[9][10][11][12][13][14][15][16][17]. Flash ADCs are widely used for high-speed operation as they have short conversion times.…”

Section: Introductionmentioning

confidence: 99%

ADC-Based Backplane Receivers: Motivations, Issues and Future

Chung¹

2016

JSTS:Journal of Semiconductor Technology and Science

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“…Because each stage of a pipelined architecture leaves a residue that only spans a fraction of the signal range, the reference levels are not fully programmable and hence cannot be used for a loop-unrolled architecture. Such a design have been shown to reach >1.5GS/s per interleaving path with FoM of 2 [11], 2.4 [10], and 0.6pJ/step [6] in 130nm, 90nm, and 65nm CMOS technology respectively. Interestingly, the stage-by-stage resolution of the input signal and the multi-cycle conversion delay enables an option of integrating a low tap-weight DFE at each stage [19].…”

Section: A Adc Architecturementioning

confidence: 99%

ADC-based serial I/O receivers

Yang¹,

Chen²

2009

2009 IEEE Custom Integrated Circuits Conference

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Fully digital receiver frontends have garnered interest for serial I/O receivers. While the speed and resolution are achievable in CMOS technologies, the challenge is to achieve low power dissipation so that the I/O links can be integrated in large ASICs. This paper describes different design techniques and shows that the power can be reduced by constraining the specifications and by making architectural trade-offs.

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“…Numerous calibration techniques for FPN compensation have been proposed in the literature [8,13,14,24,27]. These techniques can be classified according to their detection domain, calibration domain, and run-mode (see Table 1) [26].…”

Section: Introductionmentioning

confidence: 99%

A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

Reyes

Paulina²,

Sánchez³

et al. 2015

Analog Integr Circ Sig Process

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A 2-GS/s 6-bit time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 lm CMOS process. The architecture uses 8 time-interleaved track-andhold amplifiers (THA) and 16 asynchronous SAR ADCs. The sampling frequency of the TI-ADC can be set from 200 MHz to more than 2 GHz. The chip includes a programmable delay cell array to adjust up to AE25 % the sampling clock phase in each THA, and a multi-channel low voltage differential signaling interface capable of transmitting at full sampling rate (>12 Gb/s), without decimation, off-chip. These blocks make the fabricated ADC an excellent platform to test/evaluate mixed-signal calibration algorithms, which are of great interest for application in high-speed optical systems. Measurements of the fabricated ADC show a peak signal-to-noise-and-distortion ratio of 33.9 dB and a power consumption of 192 mW at 1.2 V.

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A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS

Cited by 47 publications

References 4 publications

ADC-Based Backplane Receivers: Motivations, Issues and Future

ADC-Based Backplane Receivers: Motivations, Issues and Future

ADC-based serial I/O receivers

A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

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