1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC
DOI: 10.1109/isscc.1996.488510
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A 1 W 830 MHz monolithic BiCMOS power amplifier

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Cited by 14 publications
(2 citation statements)
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“…When using bipolar technologies, the breakdown voltage is off course equal to VBceo of the nPn transistor. Therefore, our design has the second highest figure of merit for a fully integrated power amplifier, only the BICMOS design of [16] does better. We have set it equal to 10 K. From literature we selected twelve reference papers [3][4][5][15][16][17][18][19][20][21][22][23], and calculated the figure of merit for each of these PA. For this realization following numbers are being used in expression (4): P out = 0.07 W, unbalanced PAE = 25.8%, power gain = 30 dB, V breakdown = 5 V, F max = 45 GHz, f = 2.45 GHz.…”
Section: A Figure Of Merit For Saturated Pamentioning
confidence: 93%
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“…When using bipolar technologies, the breakdown voltage is off course equal to VBceo of the nPn transistor. Therefore, our design has the second highest figure of merit for a fully integrated power amplifier, only the BICMOS design of [16] does better. We have set it equal to 10 K. From literature we selected twelve reference papers [3][4][5][15][16][17][18][19][20][21][22][23], and calculated the figure of merit for each of these PA. For this realization following numbers are being used in expression (4): P out = 0.07 W, unbalanced PAE = 25.8%, power gain = 30 dB, V breakdown = 5 V, F max = 45 GHz, f = 2.45 GHz.…”
Section: A Figure Of Merit For Saturated Pamentioning
confidence: 93%
“…This is acceptable, due to the fact that the power control of the amplifier will be done by varying the DC voltage of the last stage. From [7,8] and [16] we know that this solution provides better output power and power added efficiency than a classical class E design. Therefore the Drain Efficiency (DE PA ) of the last stage is a good indicator for the PAE that will be reached.…”
Section: Design Trade-off'smentioning
confidence: 99%