High-temperature off-state and on-state characteristics of bulk-Si and thin-SO1 RESURF LDMOS transistors were studied experimentally and theoretically. The off-state leakage current in the SO1 devices was only 1.5 n A / p at 300 OC. The increase of on-resistance with temperature in the SO1 devices is smaller than in the bulk-Si devices because of the heavier doping dictated by the RESURF principle. The reverse recovery time of the SO1 device shows only slight temperature dependence. The results of this study indicate that LDMOS transistors fabricated in thin SO1 layers are well suited for high-temperature power IC applications.
A high-performance 600 V smart power technology has been developed in which novel lateral double-diffused MOS transistors (LDMOS) are merged with a BiC-MOS process flow for the construction of power integrated circuits on bonded silicon-on-insulator (BSOI) substrates. All active and passive device structures have been optimized for fabrication on BSOI layers which are less than 1.5 pm-thick, with buried oxide layers in the range of 2.0 to 3.0 pm-thick. Complete dielectric isolation processing is straightforward due to the use of a thin SO1 active device layer. A dual field plate design of the high-voltage devices results in at least a factor-of-two reduction in specific onresistance over conventional LDMOS structures for a given breakdown voltage.
This article presents results obtained using microwave reflection between 26.5 and 36.5 GHz for measuring the sheet resistance of doped layers in semiconductors. The advantage of the technique is that it is nondestructive and has a dynamic range and spatial resolution similar to what it can be obtained with four point resistivity probes. Using this technique, we have been able to measure the sheet resistance of shallow implanted layers on silicon wafers implanted with doses in the range of 1016–1012 ions/cm2. The sheet resistance measured was between 30 and 80 000 Ω/⧠.
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