A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

Henkel, Frank; Langmann, U.; Hanke, A.; Heinen, Stefan; Wagner, E.

doi:10.1109/jssc.2002.804332

Cited by 55 publications

(9 citation statements)

References 13 publications

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“…To achieve the desired signal channel selection and high image-rejection ratio (IRR), highorder IF complex bandpass filter is usually adopted, however, it would consume considerably large power. Due to its complex bandpass anti-aliasing characteristic, high dynamic range (DR) and potential for low power consumption, the continuous-time quadrature bandpass sigma-delta (CT QBP ) modulator is currently applied in low-IF multi-standard receivers [1]- [3], which could relax the requirements on the IF filter and amplifiers, therefore lowering the power consumption of the whole receiver.…”

Section: Introductionmentioning

confidence: 99%

“…The mismatch between I and Q channel would also lead to SNDR degradation [1] and emerge the image signal, and several techniques, such as quadrature mismatch scrambler (QMS) [3], inserted between the quantizer and multi-bit digital-to-analog converter (DAC), are proposed to improve the IRR, but it would contribute more ELD and increase the complexity of switches in DACs.…”

Section: Introductionmentioning

confidence: 99%

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A 5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ modulator with digital I/Q calibration for GNSS receivers

Zhang

et al. 2013

2013 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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This paper presents a dual-mode 2 nd -order, multi-bit reconfigurable continuous-time quadrature bandpass sigmadelta (CT QBP ) modulator employing power scaling technique (PST) for low-IF GNSS receivers. The proposed modulator is capable of supporting both narrow band (NB) of 5MHz bandwidth (BW) and wideband (WB) of 20MHz BW with sampling frequencies of 160MHz and 480MHz, respectively. To solve the instability issue caused by the excess loop delay (ELD) in WB mode, an additional DAC is directly feedback to the input of a summing amplifier and the ELD is fixed to half of the sampling period. Digital I/Q calibration after the decimation is employed to improve the image-rejection ratio (IRR). Implemented in 65nm CMOS, the modulator achieves 65.9/53.7dB SNDR, 76.7/65.9dB SFDR and more than 60dB IRR after calibration across 5/20MHz BW with center frequencies of 4/12MHz. Powered by a 1.2-V supply, the modulator consumes 3.5/6.8mW, resulting in FOMs of 264/516fJ/conversion.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ modulator with digital I/Q calibration for GNSS receivers

Zhang

et al. 2013

2013 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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“…The continuous-time lowpass sigma-delta (CT LP ΣΔ) modulator covers the signal bandwidth ranging from several tens of kHz up to a few MHz [1] with high signal-tonoise-plus-distortion ratio (SNDR) and acceptable power consumption, and even to several tens of MHz [2]- [3], while consuming much power to satisfy the system specifications. While used for low-IF receivers which avoid DC-offset issue, several QBP ΣΔ modulators with a few MHz bandwidth and center frequency [4], dual-mode [5] or tri-mode [6] are reported with respectable results.…”

Section: Introductionmentioning

confidence: 99%

Power-scalable multi-mode reconfigurable continuous-time lowpass/quadrature bandpass sigma-delta modulator for zero/low-IF receivers

Chi

Wang

2012

2012 IEEE International Symposium on Circuits and Systems

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A multi-mode reconfigurable wideband continuoustime lowpass/quadrature bandpass sigma-delta (CT LP/QBP ΣΔ) modulator employing power scaling technique (PST) for LTEadvanced/industry-specialized zero/low-IF receivers is presented. The proposed modulator consists of a loop filter with active-RC integrator configured as 3 rd -order lowpass or 2 ndorder complex bandpass architecture and 4-bit internal quantizer operating at 80MHz, 160MHz and 320MHz, respectively. A programmable differential current-steering DAC unit is adopted for high linearity. In LP mode, the excess loop delay is set to half the sampling period of the quantizer and an additional feedback DAC is used to maintain stability, which is not used in QBP mode. The modulator employs flexible high gain and high bandwidth amplifiers with PST to optimize power consumption among various modes. Implemented in 65nm CMOS, the modulator achieves 84.8/85.8/84.5dB SNDR, 94.9/94.1/94.6dB SFDR over 2.5/5/10-MHz signal bands in LP modes and 83.8/ 84.6dB SNDR, 94.3/96dB SFDR across 2.5/5-MHz bandwidth with programmable center frequencies of 2/4-MHz in QBP modes, respectively. Powered by a 1.2-V supply, the modulator consumes 1.8 to 4.2mW, which results in simulated FOMs of 15.5 to 27.8fJ/conversion.

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“…In recent years, several successful implementations of CT quadrature bandpass RD modulators have been presented [4][5][6][7]. In all of them, complex (polyphase) filters are needed to change the filter characteristics from DC to the intermediate frequency.…”

Section: Introductionmentioning

confidence: 99%

A one-path subsampling quadrature receiver based on a ΣΔ modulator with distributed resonators

Prefasi

Reekmans

Hernández

et al. 2011

Analog Integr Circ Sig Process

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This article presents experimental results of a quadrature bandpass sigma-delta (RD) modulator based on distributed resonators. The modulator employs transmission lines and transconductors as main components and does not require switches in the loop filter as in the case of switched-capacitor (discrete-time) filters. In addition, the proposed complex modulator does not require a quadrature mixer in the receiver. As main feature, the modulator architecture introduces an innovative way to produce the I and Q outputs that is immune to path mismatch due to the sharing of all the analog circuitry for both paths. The onebit second-order modulator ADC is able to convert IF signals at fs/2 and 3fs/2 (fs = 50 MHz), achieving an ENOB = 10 bits within a 1 MHz signal bandwidth. Therefore the modulator may be feasible for the typical IF frequencies used in cellular base stations. Furthermore, it provides an image rejection grater than 70 dB. The 0.35 lm BiCMOS chip consumes 28 mW at 3.3 V supply voltage.

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A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

Cited by 55 publications

References 13 publications

A 5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ modulator with digital I/Q calibration for GNSS receivers

A 5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ modulator with digital I/Q calibration for GNSS receivers

Power-scalable multi-mode reconfigurable continuous-time lowpass/quadrature bandpass sigma-delta modulator for zero/low-IF receivers

A one-path subsampling quadrature receiver based on a ΣΔ modulator with distributed resonators

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A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

Cited by 55 publications

References 13 publications

A 5/20MHz-BW 4.2/8.1mW CT QBP &#x03A3;&#x0394; modulator with digital I/Q calibration for GNSS receivers

A 5/20MHz-BW 4.2/8.1mW CT QBP &#x03A3;&#x0394; modulator with digital I/Q calibration for GNSS receivers

Power-scalable multi-mode reconfigurable continuous-time lowpass/quadrature bandpass sigma-delta modulator for zero/low-IF receivers

A one-path subsampling quadrature receiver based on a ΣΔ modulator with distributed resonators

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Product

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A 5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ modulator with digital I/Q calibration for GNSS receivers

A 5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ modulator with digital I/Q calibration for GNSS receivers