A 5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ modulator with digital I/Q calibration for GNSS receivers

Abstract

This paper presents a dual-mode 2 nd -order, multi-bit reconfigurable continuous-time quadrature bandpass sigmadelta (CT QBP ) modulator employing power scaling technique (PST) for low-IF GNSS receivers. The proposed modulator is capable of supporting both narrow band (NB) of 5MHz bandwidth (BW) and wideband (WB) of 20MHz BW with sampling frequencies of 160MHz and 480MHz, respectively. To solve the instability issue caused by the excess loop delay (ELD) in WB mode, an additional DAC is directly feedback to the input of a summing amplifier and the ELD is fixed to half of the sampling period. Digital I/Q calibration after the decimation is employed to improve the image-rejection ratio (IRR). Implemented in 65nm CMOS, the modulator achieves 65.9/53.7dB SNDR, 76.7/65.9dB SFDR and more than 60dB IRR after calibration across 5/20MHz BW with center frequencies of 4/12MHz. Powered by a 1.2-V supply, the modulator consumes 3.5/6.8mW, resulting in FOMs of 264/516fJ/conversion.

A 10-b Fourth-Order Quadrature Bandpass Continuous-Time $\Sigma \Delta $ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver

“…Due to the wideband characteristics of the quadrature power splitter, the I/Q matching performance of the generated I/Q input signals is not good. As a proof, the same I/Q Generator was also used to measure another sigma-delta modulator chip, and an IRR of around 30 dB before digital I/Q calibration was achieved [4]. In this work, the IRR measured with this I/Q Generator is also about 30 dB, as shown in Fig.…”

“…TABLE V compares the presented quadrature band-pass continuous-time (CT) ΣΔ modulator with the-state-of-the-art QBP CT ΣΔ modulators. [4] and [7] support multi-mode operations and only the maximum bandwidth modes are listed. Besides, the IRR in [4] is the result with the digital-calibration after the output of the modulator.…”

“…[4] and [7] support multi-mode operations and only the maximum bandwidth modes are listed. Besides, the IRR in [4] is the result with the digital-calibration after the output of the modulator. This work achieves an improved performance over a wide signal bandwidth with a relatively low FoM.…”

“…In the circuit implementation, embedded amplifiers with high gain-bandwidth product (GBW) are needed. As the amplifiers in [3] and [4] could achieve high GBW with low power consumption, their output swings are low due to the feedforward structure at the output. In this paper, a new high-frequency feedforward structure is proposed, which allows large output swing while maintaining good phase margin.…”

“…Moreover, an optimized reset-set (RS) latch is presented, which has shorter response time than the conventional RS latch (in [3] and [4]) in extreme conditions to realize a higher sampling rate. This paper is expanded from a RFIC 2015 conference paper with more details about the system-level and circuit-level design consideration and more measurement results.…”