A 1 MB, 100 MHz integrated L2 cache memory with 128b interface and ECC protection

Giacalone, G.; Busch, R.; Creed, Frank; Davidovich, A.; Divakaruni, S.M.; Drake, C.; Ematrudo, Christopher; Fifield, J.A.; Hodges, M.; Howell, Wayne J.; Jenkins, Peter; Kozyrczak, Maciek; Miller, Christopher P.; Obremski, Thomas; Reed, C.W.; Rohrbaugh, G.; Vincent, Michael; Reyn, T. von; Zimmerman, J.

doi:10.1109/isscc.1996.488721

Cited by 8 publications

(4 citation statements)

References 2 publications

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“…Historically, embedded DRAM developed from a DRAM base. Initial work at IBM and elsewhere focused on leveraging DRAM technology primarily to fabricate custom DRAMs for use in off-chip cache and graphic DRAM applications [4,5]. The main rationale for this approach was the belief that the complexity of DRAM process architecture should not be modified, and any logic functions should be contained within the available menu of devices offered by the DRAM technology.…”

Section: Migrating From the Commodity Dram Base To The Logic Basementioning

confidence: 99%

Embedded DRAM: Technology platform for the Blue Gene/L chip

et al. 2005

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The Blue Genet/L chip is a technological tour de force that embodies the system-on-a-chip concept in its entirety. This paper outlines the salient features of this 130-nm complementary metal oxide semiconductor (CMOS) technology, including the IBM unique embedded dynamic random access memory (DRAM) technology. Crucial to the execution of Blue Gene/L is the simultaneous instantiation of multiple PowerPCt cores, highperformance static random access memory (SRAM), DRAM, and several other logic design blocks on a single-platform technology. The IBM embedded DRAM platform allows this seamless integration without compromising performance, reliability, or yield. We discuss the process architecture, the key parameters of the logic components used in the processor cores and other logic design blocks, the SRAM features used in the L2 cache, and the embedded DRAM that forms the L3 cache. We also discuss the evolution of embedded DRAM technology into a higherperformance space in the 90-nm and 65-nm nodes and the potential for dynamic memory to improve overall memory subsystem performance.

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Section: Migrating From the Commodity Dram Base To The Logic Basementioning

confidence: 99%

Embedded DRAM: Technology platform for the Blue Gene/L chip

et al. 2005

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“…For instnncc, 8s a rule of thumb, for every increase of 10 degrees Celsius, the minimum refresh rate of a DRAM is roughly doubled [15]. Research in process development would be useful in this and other areas, Perhaps the best realization of processor-memory integration can be achieved in a hybrid CMOS process that incorporates the best 'features of both logic and DRAM processes.…”

Section: Future Workmentioning

confidence: 99%

The energy efficiency of IRAM architectures

Fromm

Perissakis

Cardwell

et al. 1997

Proceedings of the 24th Annual International Symposium on Computer Architecture

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Portable systems demand energy eflciency in order to maximize battery l&e. IRAM architectures, which combine DRAM anda processor on the same chip in a DRAMprocess, are more energy e$cient than conventional systems, The high density of DRAMpermits a much larger amount of memory on-chip than a traditional SRAM cache design in a logic process. This allows most or all IRAMmemory accesses to be satisfied on-chip. Thus there is much less need to drive high-capacitance off-chip buses, which contribute significantly to the energy consumption ofa system. To quanhfy this advantage we apply models of energy consumption in DRAM and SRAMmemories to results from cache simulations of applications reflective of personal productivity tasks on low power systems. We find that #AMmemory hierarchies consume as little as 22% of the energy consumed by a conventional memory hierarchy for memoryintensive applications, while delivering comparable perJormance. Furthermore, the energy consumed by a system consisting of an IRAM memory hierarchy combined with an energy eficient CPU core is as little as 40% of that of the same CPU core with a traditional memory hierarchy.

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“…Multichip module research, the basis of SiP technology, started about twenty years ago [5]. IBM has developed a CPU module, which integrated with 1M L2 cache by using MCM technology in 1996 [6]. In early 1990's, as MCM became a hot topic in CMOS society, other companies also entered into this area.…”

Section: Introductionmentioning

confidence: 99%

Area-IO DRAM/logic integration with system-in-a-package (SiP)

Wang

Dai

2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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This paper presents a cost-effective area-IO DRAM (aDRAM)/Logic integration implemented with CLC (ChipLaminate-Chip)-based System-in-a-Package (SiP) technology. By inserting 512 area-IOs into the area-IO DRAM, the bandwidth of the area-IO DRAM can achieve 10GB/s when working under 166MHz. An interface module with configurable IO width was also developed to make this implementation platform able to be adapted by various applications. A performance analysis, including bandwidth and power is also presented in this paper. It is demonstrated that area-IO DRAM/Logic integration with SiP technology provides significant cost-effective implementation methodology compared with embedded DRAM and off-chip DRAM.

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A 1 MB, 100 MHz integrated L2 cache memory with 128b interface and ECC protection

Cited by 8 publications

References 2 publications

Embedded DRAM: Technology platform for the Blue Gene/L chip

Embedded DRAM: Technology platform for the Blue Gene/L chip

The energy efficiency of IRAM architectures

Area-IO DRAM/logic integration with system-in-a-package (SiP)

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