A 1-kV 4H-SiC Power DMOSFET Optimized for Low on-Resistance

Saha, Atanu; Cooper, James A.

doi:10.1109/ted.2007.904577

Cited by 77 publications

(43 citation statements)

References 6 publications

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“…To circumvent the drawbacks brought by the low electron channel mobility, many approaches with different gate structures have also been proposed, and among them, the trench gate MOSFET (UMOSFET) is very promising. Unlike DMOSFETs, in which the cell density is limited by the horizontal JFET [5,6], UMOSFETs employ the very high cell density to minimize the contribution of channel resistance to the total on-state resistance. However, the electric field crowding at the trench gate bottom corner is a challenging issue in UMOSFETs [7,8], because the high critical electric field of 4H-SiC will bring a high electric field in the dielectrics and eventually cause long-term reliability concerns.…”

Section: Introductionmentioning

confidence: 99%

Numerical Study of 4H-SiC UMOSFETs with Split-Gate and P+ Shielding

Jiang

Zhao

et al. 2020

Energies

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In this paper, performances of a 4H-SiC UMOSFET with split gate and P+ shielding in different configurations are simulated and compared, with an emphasis on the switching characteristics and short circuit capability. A novel structure with the split gate in touch with the P+ shielding is proposed. The key design issues for 4H-SiC UMOSFETs are trench gate dielectric protection and reverse transfer capacitance Crss reduction. Based on simulation results, it is concluded that a UMOSFET with a gate structure combining split gate grounded to the trench bottom protection P+ shielding layer and a current spreading layer is achieved to yield the best compromise between conduction, switching, and short circuit performance. The split-gate design can effectively reduce Crss by shielding the coupling between the gate electrode and the drain region. The P+ shielding design not only protects the oxide at trench bottom corners but also minimizes the short channel effect due to drain-induced barrier lowing and the channel length modulation. Trade-off of the doping concentration of current spreading layer for UMOSFET is also discussed. A heavily doped current spreading layer may increase Crss and influence the switching time, even though RON,SP is reduced.

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Section: Introductionmentioning

confidence: 99%

Numerical Study of 4H-SiC UMOSFETs with Split-Gate and P+ Shielding

Jiang

Zhao

et al. 2020

Energies

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“…However, despite the major advancements in SiC process technology during the last decade, the realization of SiC MOSFETs is still hindered due largely to the low inversion channel mobility. The problem caused by the high interface state density at the metal-oxide-semiconductor (MOS) interface of SiO 2 /SiC is the same as that of the early silicon devices [3,4]. On the other hand, one of the major differences between Si and SiC is the energy barrier height between the semiconductor and dielectrics, thus the tunneling current density through the oxide is higher in SiC than that in Si for the same surface electric field [5].…”

Section: Introductionmentioning

confidence: 99%

“…Increasing the SiO 2 /SiC interface charges may lead to a decreased breakdown voltage and therefore the interface charges in SiC MOSFETs can significantly affect the transient characteristics as well as the static characteristics. Although various SiC DMOSFET structures have been reported so far for optimizing performances [6], the effect of the interface states on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report on the effect of interface charge density (D it ) distributions on the transient characteristics of the SiC DMOSFET devices.…”

Section: Introductionmentioning

confidence: 99%

Impact of Interface Charges on the Transient Characteristics of 4H-SiC DMOSFETs

Kang¹,

Bahng²,

Kim

et al. 2012

Journal of Electrical Engineering and Technology

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-In this paper, we study the transient characteristics of 4H-SiC DMOSFETs with different interface charges to improve the turn-on rising time. A physics-based two-dimensional mixed device and circuit simulator was used to understand the relationship between the switching characteristics and the physical device structures. As the SiO 2 /SiC interface charge increases, the current density is reduced and the switching time is increased, which is due primarily to the lowered channel mobility. The result of the switching performance is shown as a function of the gate-to-source capacitance and the channel resistance. The results show that the switching performance of the 4H-SiC DMOSFET is sensitive to the channel resistance that is affected by the interface charge variations, which suggests that it is essential to reduce the interface charge densities in order to improve the switching speed in 4H-SiC DMOSFETs.

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“…경에서 안정함을 보인다 [3]. 그러므로, 탄화규소 (SiC) 소재를 이용한 소자는 고온에서 안정적으로 동작하며 높은 전력 범위를 가지는 소자로서 효율을 높이기 위해 여러 가지 소자구조에 대하여 연구 개발이 활발히 진행 중에 있다 [4,5].…”

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Temperature Dependence of Neutron Irradiated SiC Schottky Diode

Kim¹,

Koo

2014

Journal of the Korean Institute of Electrical and Electronic Ma

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Abstract:The temperature dependent characteristics on the properties of SiC Schottky Diode has been investigated. In this study, the temperature dependent current-voltage characteristics of the SiC Schottky diode were measured in the range of 300 ∼ 500 K. Divided into pre-and post-irradiated device was measured. The barrier height after irradiation device at 500 K increased 0.15 eV compared to 300 K, the barrier height of pre-neutron irradiated Schottky diode increased 0.07 eV. The effective barrier height after irradiation increased from 0.89 eV to 1.05 eV. And ideality factor of neutron irradiated Schottky diode at 500 K decreased 0.428 compared to 300 K, the ideality factor of pre-neutron irradiated Schottky diode decreased 0.354. Also, a slight positive shift in threshold voltage from 0.53 to 0.68 V. we analyzed the effective barrier height and ideality factor of SiC Schottky diode as function of temperature.

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A 1-kV 4H-SiC Power DMOSFET Optimized for Low on-Resistance

Cited by 77 publications

References 6 publications

Numerical Study of 4H-SiC UMOSFETs with Split-Gate and P+ Shielding

Numerical Study of 4H-SiC UMOSFETs with Split-Gate and P+ Shielding

Impact of Interface Charges on the Transient Characteristics of 4H-SiC DMOSFETs

Temperature Dependence of Neutron Irradiated SiC Schottky Diode

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