Abstract:An embedded DRAM (eDRAM) integrated into 22 nm CMOS logic technology using tri-gate high-k metal gate transistor and MIM capacitor is described. A 1 Gb eDRAM die is designed, which includes fully integrated programmable charge pumps to over-and underdrive wordlines with output voltage regulation. The die area is 77 mm and provides 64 GB/s Read and 64 GB/s Write at 1.05 V. 100 µs retention time is achieved at 95°C using the worst case memory array stress patterns. The 1 Gb eDRAM die is multi-chip-packaged with … Show more
“…We report power for a 1.28GHz operating frequency, which is fast enough to achieve physics-limited volume rates for the full 32×32 receive aperture at any imaging depth; smaller apertures can be processed at lower frequencies (and lower power). We estimate the area and power requirements of the 12.5MB eDRAM based on reported results for a 22nm technology [4].…”
High volume acquisition rates are imperative for medical ultrasound imaging applications, such as 3D elastography and 3D vector flow imaging. Unfortunately, despite recent algorithmic improvements, high-volume-rate imaging remains computationally infeasible on known platforms. In this paper, we propose Tetris, a novel hardware accelerator for ultrasound beamforming that enables volume acquisition rates up to the physics limits of acoustic propagation delay. Through algorithmic and hardware optimizations, we enable a streaming system design outclassing previously proposed accelerators in performance while lowering hardware complexity and storage requirements. For a representative imaging task, our proposed system generates physics-limited 13,020 volumes per second in a 2.5W power budget. CCS CONCEPTS • Hardware → Emerging architectures; 3D integrated circuits.;
“…We report power for a 1.28GHz operating frequency, which is fast enough to achieve physics-limited volume rates for the full 32×32 receive aperture at any imaging depth; smaller apertures can be processed at lower frequencies (and lower power). We estimate the area and power requirements of the 12.5MB eDRAM based on reported results for a 22nm technology [4].…”
High volume acquisition rates are imperative for medical ultrasound imaging applications, such as 3D elastography and 3D vector flow imaging. Unfortunately, despite recent algorithmic improvements, high-volume-rate imaging remains computationally infeasible on known platforms. In this paper, we propose Tetris, a novel hardware accelerator for ultrasound beamforming that enables volume acquisition rates up to the physics limits of acoustic propagation delay. Through algorithmic and hardware optimizations, we enable a streaming system design outclassing previously proposed accelerators in performance while lowering hardware complexity and storage requirements. For a representative imaging task, our proposed system generates physics-limited 13,020 volumes per second in a 2.5W power budget. CCS CONCEPTS • Hardware → Emerging architectures; 3D integrated circuits.;
“…Four of the eight 16 MB macros operate in parallel to deliver a cache line read or write each 1.6 GHz clock cycle. Retention time is 100 S at 93C, 1.0 V, and the 77 mm die (including charge pumps and associated supply regulators) achieves a density of 17.5 Mb/mm [5].…”
Section: Embedded-dram and On-package I/omentioning
We describe the 4th Generation Intel® Core™ processor family (codenamed "Haswell") implemented on Intel® 22 nm technology and intended to support form factors from desktops to fan-less Ultrabooks™. Performance enhancements include a 102 GB/sec L4 eDRAM cache, hardware support for transactional synchronization, and new FMA instructions that double FP operations per clock. Power improvements include Fully-Integrated Voltage Regulators ( 50% battery life extension), new low-power states (95% standby power savings), optimized MCP I/O system (1.0-1.22 pJ/b), and improved DDR I/O circuits (40% active and 100x idle power savings). Other improvements include full-platform optimization via integrated display I/O interfaces.
“…Since gain-cell based eDRAM offers several advantages [8], registers (SRAMs partitioned into smaller banks) are replaced with non-refresh eDRAMs in the LDPC decoder. However, unlike cache applications [6]- [14], the replacement of small SRAM banks can be impractical, since the hardware overhead of additional supply voltages or voltage regulators (or charge pumps) for stable write operation and reference voltage generation in eDRAM can overshadow its inherent advantages.…”
This paper presents a Viterbi-specific 2T gain cellbased embedded DRAM (eDRAM) design for IEEE 802.11n WLAN application. In the proposed Viterbi decoder, refresh operations are completely removed in the eDRAM, by ensuring that the read-after-write period of survivor memory is shorter than the retention time of the gain cell. In order to facilitate the write operation with single-supply voltage, a beneficial read word-line (RWL) coupling technique is proposed. In this work, we also present a reference voltage generation scheme to support single-ended read operation. Thanks to the decoupled read and write structure of the gain cell, the proposed eDRAM can support dual-port operations without large area overhead, thus doubling the bandwidth of memories in the Viterbi decoder. To further reduce the area of the customized Viterbi memory, common redundant hardware between the memory peripheral and computational logics is identified and eliminated without latency overhead. The 4 bit soft-decision 64-state Viterbi decoder with 24 kb eDRAM (1-bank) is implemented in 65 nm CMOS process technology. The chip measurement results show 44% area and 39% power savings over the conventional SRAM-based Viterbi decoder implementation.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.