A 1.9-μm/sup 2/ loadless CMOS four-transistor SRAM cell in a 0.18-μm logic technology

Noda, K.; Matsui, K.; Imai, K.; Inoue, Ken; Tokashiki, K.; Kawamoto, H.; Yoshida, Kakunoshin; Takeda, Koichi; Nakamura, N.; Kimura, Takahiro; Toyoshima, Hideo; Koishikawa, Yohei; Maruyama, Satoshi; Saitoh, T.; Tanigawa, T.

doi:10.1109/iedm.1998.746440

Cited by 3 publications

(2 citation statements)

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“…Reducing cell area is the greatest concern in SRAMs, as is suggested by the on-chip, 3-MB, L3 cache [6]. The loadless CMOS, 4-T SRAM [42] shows promise because the cell area is only 56% of that of the 6-T cell. However, it suffers from the data-pattern problem, and it is difficult to accurately control the nonselected word-line voltage to maintain the load current.…”

Section: Sram Cellsmentioning

confidence: 99%

Review and future prospects of low-voltage RAM circuits

et al. 2003

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This paper describes low-voltage random-access memory (RAM) cells and peripheral circuits for standalone and embedded RAMs, focusing on stable operation and reduced subthreshold current in standby and active modes. First, technology trends in low-voltage dynamic RAMs (DRAMs) and static RAMs (SRAMs) are reviewed and the challenges of lowvoltage RAMs in terms of cell signal charge are clarified, including the necessary threshold voltage, V T , and its variations in the MOS field-effect transistors (MOSFETs) of RAM cells and sense amplifiers, leakage currents (subthreshold current and gate-tunnel current), and speed variations resulting from design parameter variations. Second, developments in conventional RAM cells and emerging cells, such as DRAM gain cells and leakage-immune SRAM cells, are discussed from the viewpoints of cell area, operating voltage, and leakage currents of MOSFETs. Third, the concepts proposed to date to reduce subthreshold current and the advantages of RAMs with respect to reducing the subthreshold current are summarized, including their applications to RAM circuits to reduce the current in standby and active modes, exemplified by DRAMs. After this, design issues in other peripheral circuits, such as sense amplifiers and low-voltage supporting circuits, are discussed, as are power management to suppress speed variations and reduce the power of power-aware systems, and testing. Finally, future prospects based on the above discussion are examined.

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Section: Sram Cellsmentioning

confidence: 99%

Review and future prospects of low-voltage RAM circuits

et al. 2003

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“…Furthermore, they have a higher SNM and a lower sensitivity to Vth fluctuations [198]. To date, several 4T SRAM structures have been reported in literature [165,[194][195][196][198][199][200][201][202][203][204][205][206][207], three of which [194][195][196]203,207] are presented in Fig. 2 [196] The first conventional 5T SRAM cell was introduced in 1988 by Yang et.…”

Section: T Sram Cellmentioning

confidence: 99%

Design of low-voltage low-power nano-scale SRAMs

Tuan¹

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Static Random Access Memory (SRAM)-based cache is one of the most important components of state-of-the-art VLSI systems. It is responsible for increasing the speed of data flows, and hence the speed of the whole electronic system. SRAM is prevalently utilized in the design of modern microprocessors for bridging the widening divergence between the performances of the Central Processing Unit (CPU) and the Dynamic RAM (DRAM)-based main memory. This trend is accentuated by the never-ending market demand for sophisticated communication and multimedia applications, which require high-tech portable electronic gadgets with high-performance as the requisite feature. As the on-chip memory occupies a large portion of the chip area, the power dissipated within the memory, both active and standby, will become a dominant part of the chip's total power consumption. In view of the above, there is invariably an apparent urgency to address these two often-conflicting power and performance requirements. Our research focuses on SRAM cell design for ultra low-voltage ultra low-power applications. Two SRAM cell topologies have been proposed with an improved noise margin and hence can operate at very low supply voltages to save power. Our first proposal is a 10T SRAM cell design that has 4x read and lox leakage power reduction when compared to the conventional 6T design. The proposed cell has separate readwrite ports and hence its read noise margin is 31% higher than that of the conventional 6T design. We also proposed a special read scheme that accesses only one cell during read out and hence more than 98% of cell active current is saved (assuming that each row has 128 cells and operating frequency is 250 MHz). This hefty amount of power reduction is obtained at the cost of 33% cell area overhead and 23% of write-ability. Extensive simulations on two SRAM macros using a standard 65nm / 1V CMOS process showed that the total read power consumption of the proposed design has reduced to 25% of that of the conventional 6T design. It also has smaller write power consumption. More

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Memories

Veendrick

2024

Nanometer CMOS ICs

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A 1.9-μm/sup 2/ loadless CMOS four-transistor SRAM cell in a 0.18-μm logic technology

Cited by 3 publications

References 4 publications

Review and future prospects of low-voltage RAM circuits

Review and future prospects of low-voltage RAM circuits

Design of low-voltage low-power nano-scale SRAMs

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