A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit

Liu, Po-Chun; Chang, Hsie-Chia; Lee, Chen‐Yi

doi:10.1109/esscirc.2009.5326020

Cited by 16 publications

(10 citation statements)

References 5 publications

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“…Our architecture employs only one 128-bit 4-in-1 multiplexer, whereas conventional ones employ several 128-bit multiplexers. For example, the datapath in [21] employs seven 128-bit multiplexers. 1 Fewer selectors can reduce the critical path delay and circuit area and solve the false critical path problem.…”

Section: Round Function Partmentioning

confidence: 99%

“…2. Some architectures such as [9], [21] unify AddInitialKey and AddRoundKeys. We did not unify them to avoid increasing the number of selectors.…”

Section: Round Function Partmentioning

confidence: 99%

“…1. However, conventional key scheduling datapaths such those as in [9], [21] are not applicable to our architecture because they have a loop with a false path and/or a longer true critical path than our optimized round datapath.…”

Section: Key Scheduling Partmentioning

confidence: 99%

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High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

Ueno

Homma²,

Morioka

et al. 2020

IEEE Trans. Comput.

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This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and InvSubBytes without any delay overhead. In addition, a new optimization technique for minimizing linear mappings, named multiplicative-offset, further enhances the hardware efficiency. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and is the most efficient in terms of throughput per area among conventional AES encryption/decryption and encryption architectures with tower-field S-boxes. The proposed round-based architecture can perform AES encryption where block-wise parallelism is unavailable (e.g., cipher block chaining (CBC) mode); thus, our techniques can be globally applied to any type of architecture including pipelined ones. We evaluated the performance of the proposed and some conventional datapaths by logic synthesis with the NanGate 45-nm open-cell library. As a result, we can confirm that our proposed architectures achieve approximately 51-64 percent higher efficiency (i.e., higher bps/GE) and lower power/energy consumption than the other conventional counterparts.

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Section: Round Function Partmentioning

confidence: 99%

“…2. Some architectures such as [9], [21] unify AddInitialKey and AddRoundKeys. We did not unify them to avoid increasing the number of selectors.…”

Section: Round Function Partmentioning

confidence: 99%

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High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

Ueno

Homma²,

Morioka

et al. 2020

IEEE Trans. Comput.

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“…During decryption, these operations are reversed by inverting the arithmetic computations and permute transformations performed on the plain-text bytes in the encryption process. Conventional hardware accelerators use a 128 bit datapath organized as 16 byte-slices with 64 wiring tracks for the ShiftRows permutations to achieve single-cycle round latency, and 10-cycle throughput [2]- [5]. Higher throughput can be achieved by pipelining multiple back-to-back round hardware [6].…”

Section: ) 2 Polynomials In 22 Nmmentioning

confidence: 99%

340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS

Mathew

Satpathy

Suresh

et al. 2015

IEEE J. Solid-State Circuits

111

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This paper describes an on-die lightweight nanoAES hardware accelerator, fabricated in 22 nm tri-gate high-k/metal-gate CMOS, targeted for ultra-low power symmetric-key encryption and decryption on mobile SOCs. Compared to conventional 128 bit AES implementations, this design uses a single 8 bit Sbox circuit along with ShiftRows byte-order data processing to compute all AES rounds in native composite-field. This approach along with a serial-accumulating MixColumns circuit, area-optimized encrypt and decrypt Galois-field polynomials and integrated on-the-fly key generation circuit results in a compact encrypt/decrypt layout occupying 2200/2736 m and lowest-reported gate count of 1947/2090 respectively, while achieving: (i) maximum operating frequency of 1.133 GHz and total power consumption of 13 mW with leakage component of 500 W, measured at 0.9 V, 25 C, (ii) nominal AES-128 encrypt/decrypt throughput of 432/671 Mbps respectively, with peak energy-efficiency of 289 Gbps/W measured at near-threshold operation of 430 mV (11 higher than previously reported implementations), (iii) encrypt/decrypt latencies of 336/216 cycles and total energy consumption of 3.9/2.5 nJ respectively, (iv) wide operating supply voltage range with robust sub-threshold voltage performance of 45 Mbps, 170 W, measured at 340 mV, 25 C and (v) first-reported Galois-field polynomial-based micro-architectural co-optimization, resulting in distinct area-optimized encrypt and decrypt polynomials with up to 9% area reduction at iso-performance.Index Terms-Advanced encryption standard, composite-field polynomial arithmetic, encryption hardware accelerator, lightweight crypto, on-the-fly key-generation, security, ultra-low power AES.

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“…3 shows the crypto core design. The biomedical data is encrypted by AES-128 designed in [7]. Additionally, the ECC-163 processor with SHA-256 hash function is integrated for key exchange and user identification protocols in mobile environment.…”

Section: B Risc Corementioning

confidence: 99%

A micropower biomedical signal processor for mobile healthcare applications

Hsu

Chen

Chang

et al. 2011

IEEE Asian Solid-State Circuits Conference 2011

Self Cite

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This work presents a biomedical signal processor (BSP) with hybrid functional cores to optimize the power dissipation and system flexibility for mobile healthcare applications. Embedded with the biomedical core and a 32-bit RISC core, multi-features are extracted for classification and the abnormal data are compressed. In addition, the crypto core secures both the data and wireless link protocols to protect the user privacy. This BSP chip is fabricated in a 90nm standard CMOS technology with core area of 1.17mm 2 . To overcome the leakage in advanced technology, a duty-cycled clock generator minimizes the system active duty and the inactive functions are power gated. Operating at 25MHz frequency and 0.5V supply voltage, the energy of RISC core is down to 3.44pJ/cycle. Accompanied with dedicated biomedical and crypto cores, the average BSP power achieves 38µW at 25MHz and 0.5/1.0V when performing the ECG alarm application.

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A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit

Cited by 16 publications

References 5 publications

High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS

A micropower biomedical signal processor for mobile healthcare applications

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